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8288445: AArch64: C2 compilation fails with guarantee(!true || (true …
…&& (shift != 0))) failed: impossible encoding

Reviewed-by: phh
Backport-of: b4490386fe348250e88347526172c1c27ef01eba
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William Kemper authored and Paul Hohensee committed Oct 20, 2022
1 parent 5465105 commit a2b2a22
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Showing 2 changed files with 97 additions and 14 deletions.
38 changes: 24 additions & 14 deletions src/hotspot/cpu/aarch64/aarch64.ad
Expand Up @@ -4440,6 +4440,16 @@ operand immFPacked()
interface(CONST_INTER);
%}

operand immI_positive()
%{
predicate(n->get_int() > 0);
match(ConI);

op_cost(0);
format %{ %}
interface(CONST_INTER);
%}

// Narrow pointer operands
// Narrow Pointer Immediate
operand immN()
Expand Down Expand Up @@ -17432,7 +17442,7 @@ instruct vsll16B_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
instruct vsra8B_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
match(Set dst (RShiftVB src shift));
Expand All @@ -17447,7 +17457,7 @@ instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
instruct vsra16B_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (RShiftVB src shift));
ins_cost(INSN_COST);
Expand All @@ -17461,7 +17471,7 @@ instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
instruct vsrl8B_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
match(Set dst (URShiftVB src shift));
Expand All @@ -17481,7 +17491,7 @@ instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl16B_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (URShiftVB src shift));
ins_cost(INSN_COST);
Expand Down Expand Up @@ -17636,7 +17646,7 @@ instruct vsll8S_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
instruct vsra4S_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (RShiftVS src shift));
Expand All @@ -17651,7 +17661,7 @@ instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
instruct vsra8S_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (RShiftVS src shift));
ins_cost(INSN_COST);
Expand All @@ -17665,7 +17675,7 @@ instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
instruct vsrl4S_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (URShiftVS src shift));
Expand All @@ -17685,7 +17695,7 @@ instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl8S_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (URShiftVS src shift));
ins_cost(INSN_COST);
Expand Down Expand Up @@ -17824,7 +17834,7 @@ instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
instruct vsra2I_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (RShiftVI src shift));
ins_cost(INSN_COST);
Expand All @@ -17837,7 +17847,7 @@ instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
instruct vsra4I_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (RShiftVI src shift));
ins_cost(INSN_COST);
Expand All @@ -17850,7 +17860,7 @@ instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
instruct vsrl2I_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (URShiftVI src shift));
ins_cost(INSN_COST);
Expand All @@ -17863,7 +17873,7 @@ instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl4I_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (URShiftVI src shift));
ins_cost(INSN_COST);
Expand Down Expand Up @@ -17936,7 +17946,7 @@ instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
instruct vsra2L_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (RShiftVL src shift));
ins_cost(INSN_COST);
Expand All @@ -17949,7 +17959,7 @@ instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl2L_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (URShiftVL src shift));
ins_cost(INSN_COST);
Expand Down
73 changes: 73 additions & 0 deletions test/hotspot/jtreg/compiler/codegen/ShiftByZero.java
@@ -0,0 +1,73 @@
/*
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/

/*
* @test
* @bug 8288445
* @summary Test shift by 0
* @run main/othervm -Xbatch -XX:-TieredCompilation
* compiler.codegen.ShiftByZero
*/

package compiler.codegen;

public class ShiftByZero {

public static final int N = 64;

public static int[] i32 = new int[N];

public static void bMeth() {
int shift = i32[0];
// This loop is to confuse the optimizer, so that "shift" is
// optimized to 0 only after loop vectorization.
for (int i8 = 279; i8 > 1; --i8) {
shift <<= 6;
}
// low 6 bits of shift are 0, so shift can be
// simplified to constant 0
{
for (int i = 0; i < N; ++i) {
i32[i] += i32[i] >>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] += i32[i] >>>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] >>>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] >>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] <<= shift;
}
}
}

public static void main(String[] strArr) {
for (int i = 0; i < 20_000; i++) {
bMeth();
}
}
}

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