8288467: remove memory_operand assert for spilled instructions

Reviewed-by: stuefe
Backport-of: af05139133530871c88991aa0340205cfc44972a

Author: GoeLin

src/hotspot/share/opto/chaitin.cpp

@@ -1693,8 +1693,13 @@ void PhaseChaitin::fixup_spills() {
             // instructions which have "stackSlotX" parameter instead of "memory".
             // For example, "MoveF2I_stack_reg". We always need a memory edge from
             // src to cisc, else we might schedule cisc before src, loading from a
-            // spill location before storing the spill.
-            assert(cisc->memory_operand() == NULL, "no memory operand, only stack");
+            // spill location before storing the spill. On some platforms, we land
+            // in this else case because mach->oper_input_base() > 1, i.e. we have
+            // multiple inputs. In some rare cases there are even multiple memory
+            // operands, before and after spilling.
+            // (e.g. spilling "addFPR24_reg_mem" to "addFPR24_mem_cisc")
+            // In either case, there is no space in the inputs for the memory edge
+            // so we add an additional precedence / memory edge.
             cisc->add_prec(src);
           }
           block->map_node(cisc, j);          // Insert into basic block