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1 | 1 | //
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2 |
| -// Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. |
| 2 | +// Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved. |
3 | 3 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 | 4 | //
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5 | 5 | // This code is free software; you can redistribute it and/or modify it
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@@ -7822,9 +7822,9 @@ instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
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7822 | 7822 | %}
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7823 | 7823 |
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7824 | 7824 | // Divide Register Long
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7825 |
| -instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ |
| 7825 | +instruct divL_eReg(eADXRegL dst, eRegL src1, eRegL src2) %{ |
7826 | 7826 | match(Set dst (DivL src1 src2));
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7827 |
| - effect( KILL cr, KILL cx, KILL bx ); |
| 7827 | + effect(CALL); |
7828 | 7828 | ins_cost(10000);
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7829 | 7829 | format %{ "PUSH $src1.hi\n\t"
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7830 | 7830 | "PUSH $src1.lo\n\t"
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@@ -7870,9 +7870,9 @@ instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
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7870 | 7870 | %}
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7871 | 7871 |
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7872 | 7872 | // Remainder Register Long
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7873 |
| -instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ |
| 7873 | +instruct modL_eReg(eADXRegL dst, eRegL src1, eRegL src2) %{ |
7874 | 7874 | match(Set dst (ModL src1 src2));
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7875 |
| - effect( KILL cr, KILL cx, KILL bx ); |
| 7875 | + effect(CALL); |
7876 | 7876 | ins_cost(10000);
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7877 | 7877 | format %{ "PUSH $src1.hi\n\t"
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7878 | 7878 | "PUSH $src1.lo\n\t"
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