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8260585: AArch64: Wrong code generated for shifting right and accumul…
…ating four unsigned short integers

Reviewed-by: iveresov, dlong, njian, aph
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Dong Bo authored and dean-long committed Feb 3, 2021
1 parent 1a7040e commit 5307afa9e71592c396f64a91262819e6f918da4e
Showing with 463 additions and 21 deletions.
  1. +5 −21 src/hotspot/cpu/aarch64/aarch64.ad
  2. +458 −0 test/hotspot/jtreg/compiler/c2/TestShiftRightAndAccumulate.java
@@ -18855,11 +18855,7 @@ instruct vsrla8B_imm(vecD dst, vecD src, immI shift) %{
format %{ "usra $dst, $src, $shift\t# vector (8B)" %}
ins_encode %{
int sh = (int)$shift$$constant;
if (sh >= 8) {
__ eor(as_FloatRegister($src$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
} else {
if (sh < 8) {
__ usra(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg), sh);
}
@@ -18874,11 +18870,7 @@ instruct vsrla16B_imm(vecX dst, vecX src, immI shift) %{
format %{ "usra $dst, $src, $shift\t# vector (16B)" %}
ins_encode %{
int sh = (int)$shift$$constant;
if (sh >= 8) {
__ eor(as_FloatRegister($src$$reg), __ T16B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
} else {
if (sh < 8) {
__ usra(as_FloatRegister($dst$$reg), __ T16B,
as_FloatRegister($src$$reg), sh);
}
@@ -18893,12 +18885,8 @@ instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
format %{ "usra $dst, $src, $shift\t# vector (4H)" %}
ins_encode %{
int sh = (int)$shift$$constant;
if (sh >= 16) {
__ eor(as_FloatRegister($src$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
} else {
__ ushr(as_FloatRegister($dst$$reg), __ T4H,
if (sh < 16) {
__ usra(as_FloatRegister($dst$$reg), __ T4H,
as_FloatRegister($src$$reg), sh);
}
%}
@@ -18912,11 +18900,7 @@ instruct vsrla8S_imm(vecX dst, vecX src, immI shift) %{
format %{ "usra $dst, $src, $shift\t# vector (8H)" %}
ins_encode %{
int sh = (int)$shift$$constant;
if (sh >= 16) {
__ eor(as_FloatRegister($src$$reg), __ T16B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
} else {
if (sh < 16) {
__ usra(as_FloatRegister($dst$$reg), __ T8H,
as_FloatRegister($src$$reg), sh);
}

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