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8269879: [PPC64] C2: Math.rint intrinsic uses wrong rounding mode
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Reviewed-by: lucy, goetz
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TheRealMDoerr committed Jul 7, 2021
1 parent 7fcd5ca commit 1f2bf1d
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Showing 3 changed files with 7 additions and 2 deletions.
2 changes: 2 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
Expand Up @@ -576,6 +576,7 @@ class Assembler : public AbstractAssembler {
XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT | 209u << 3),
XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT | 241u << 3),
XVRDPI_OPCODE = (60u << OPCODE_SHIFT | 201u << 2),
XVRDPIC_OPCODE = (60u << OPCODE_SHIFT | 235u << 2),
XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2),
XVRDPIP_OPCODE = (60u << OPCODE_SHIFT | 233u << 2),

Expand Down Expand Up @@ -2384,6 +2385,7 @@ class Assembler : public AbstractAssembler {
inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xvrdpi( VectorSRegister d, VectorSRegister b);
inline void xvrdpic( VectorSRegister d, VectorSRegister b);
inline void xvrdpim( VectorSRegister d, VectorSRegister b);
inline void xvrdpip( VectorSRegister d, VectorSRegister b);

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1 change: 1 addition & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
Expand Up @@ -848,6 +848,7 @@ inline void Assembler::xvmsubadp( VectorSRegister d, VectorSRegister a, VectorSR
inline void Assembler::xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVNMSUBASP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVNMSUBADP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvrdpi( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPI_OPCODE | vsrt(d) | vsrb(b)); }
inline void Assembler::xvrdpic( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIC_OPCODE | vsrt(d) | vsrb(b)); }
inline void Assembler::xvrdpim( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIM_OPCODE | vsrt(d) | vsrb(b)); }
inline void Assembler::xvrdpip( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIP_OPCODE | vsrt(d) | vsrb(b)); }

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6 changes: 4 additions & 2 deletions src/hotspot/cpu/ppc/ppc.ad
Expand Up @@ -2108,6 +2108,8 @@ const bool Matcher::match_rule_supported(int opcode) {
switch (opcode) {
case Op_SqrtD:
return VM_Version::has_fsqrt();
case Op_RoundDoubleMode:
return VM_Version::has_vsx();
case Op_CountLeadingZerosI:
case Op_CountLeadingZerosL:
return UseCountLeadingZerosInstructionsPPC64;
Expand Down Expand Up @@ -13961,7 +13963,7 @@ instruct roundD_reg(regD dst, regD src, immI8 rmode) %{
ins_encode %{
switch ($rmode$$constant) {
case RoundDoubleModeNode::rmode_rint:
__ frin($dst$$FloatRegister, $src$$FloatRegister);
__ xvrdpic($dst$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr());
break;
case RoundDoubleModeNode::rmode_floor:
__ frim($dst$$FloatRegister, $src$$FloatRegister);
Expand All @@ -13985,7 +13987,7 @@ instruct vround2D_reg(vecX dst, vecX src, immI8 rmode) %{
ins_encode %{
switch ($rmode$$constant) {
case RoundDoubleModeNode::rmode_rint:
__ xvrdpi($dst$$VectorSRegister, $src$$VectorSRegister);
__ xvrdpic($dst$$VectorSRegister, $src$$VectorSRegister);
break;
case RoundDoubleModeNode::rmode_floor:
__ xvrdpim($dst$$VectorSRegister, $src$$VectorSRegister);
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