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8267652: c2 loop unrolling by 8 results in reading memory past array
Reviewed-by: sviswanathan, kvn, vlivanov
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Nils Eliasson committed Jun 22, 2021
1 parent 578c55b commit dc12cb7
Showing 1 changed file with 49 additions and 22 deletions.
71 changes: 49 additions & 22 deletions src/hotspot/cpu/x86/x86.ad
Expand Up @@ -4844,7 +4844,8 @@ instruct vaddB_reg(vec dst, vec src1, vec src2) %{
%}

instruct vaddB_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVB src (LoadVector mem)));
format %{ "vpaddb $dst,$src,$mem\t! add packedB" %}
ins_encode %{
Expand Down Expand Up @@ -4877,7 +4878,8 @@ instruct vaddS_reg(vec dst, vec src1, vec src2) %{
%}

instruct vaddS_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVS src (LoadVector mem)));
format %{ "vpaddw $dst,$src,$mem\t! add packedS" %}
ins_encode %{
Expand Down Expand Up @@ -4911,7 +4913,8 @@ instruct vaddI_reg(vec dst, vec src1, vec src2) %{


instruct vaddI_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVI src (LoadVector mem)));
format %{ "vpaddd $dst,$src,$mem\t! add packedI" %}
ins_encode %{
Expand Down Expand Up @@ -4944,7 +4947,8 @@ instruct vaddL_reg(vec dst, vec src1, vec src2) %{
%}

instruct vaddL_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVL src (LoadVector mem)));
format %{ "vpaddq $dst,$src,$mem\t! add packedL" %}
ins_encode %{
Expand Down Expand Up @@ -4977,7 +4981,8 @@ instruct vaddF_reg(vec dst, vec src1, vec src2) %{
%}

instruct vaddF_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVF src (LoadVector mem)));
format %{ "vaddps $dst,$src,$mem\t! add packedF" %}
ins_encode %{
Expand Down Expand Up @@ -5010,7 +5015,8 @@ instruct vaddD_reg(vec dst, vec src1, vec src2) %{
%}

instruct vaddD_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AddVD src (LoadVector mem)));
format %{ "vaddpd $dst,$src,$mem\t! add packedD" %}
ins_encode %{
Expand Down Expand Up @@ -5045,7 +5051,8 @@ instruct vsubB_reg(vec dst, vec src1, vec src2) %{
%}

instruct vsubB_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVB src (LoadVector mem)));
format %{ "vpsubb $dst,$src,$mem\t! sub packedB" %}
ins_encode %{
Expand Down Expand Up @@ -5079,7 +5086,8 @@ instruct vsubS_reg(vec dst, vec src1, vec src2) %{
%}

instruct vsubS_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVS src (LoadVector mem)));
format %{ "vpsubw $dst,$src,$mem\t! sub packedS" %}
ins_encode %{
Expand Down Expand Up @@ -5112,7 +5120,8 @@ instruct vsubI_reg(vec dst, vec src1, vec src2) %{
%}

instruct vsubI_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVI src (LoadVector mem)));
format %{ "vpsubd $dst,$src,$mem\t! sub packedI" %}
ins_encode %{
Expand Down Expand Up @@ -5146,7 +5155,8 @@ instruct vsubL_reg(vec dst, vec src1, vec src2) %{


instruct vsubL_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVL src (LoadVector mem)));
format %{ "vpsubq $dst,$src,$mem\t! sub packedL" %}
ins_encode %{
Expand Down Expand Up @@ -5179,7 +5189,8 @@ instruct vsubF_reg(vec dst, vec src1, vec src2) %{
%}

instruct vsubF_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVF src (LoadVector mem)));
format %{ "vsubps $dst,$src,$mem\t! sub packedF" %}
ins_encode %{
Expand Down Expand Up @@ -5212,7 +5223,8 @@ instruct vsubD_reg(vec dst, vec src1, vec src2) %{
%}

instruct vsubD_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (SubVD src (LoadVector mem)));
format %{ "vsubpd $dst,$src,$mem\t! sub packedD" %}
ins_encode %{
Expand Down Expand Up @@ -5360,7 +5372,8 @@ instruct vmulS_reg(vec dst, vec src1, vec src2) %{
%}

instruct vmulS_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVS src (LoadVector mem)));
format %{ "vpmullw $dst,$src,$mem\t! mul packedS" %}
ins_encode %{
Expand Down Expand Up @@ -5394,7 +5407,8 @@ instruct vmulI_reg(vec dst, vec src1, vec src2) %{
%}

instruct vmulI_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVI src (LoadVector mem)));
format %{ "vpmulld $dst,$src,$mem\t! mul packedI" %}
ins_encode %{
Expand All @@ -5418,7 +5432,8 @@ instruct vmulL_reg(vec dst, vec src1, vec src2) %{
%}

instruct vmulL_mem(vec dst, vec src, memory mem) %{
predicate(VM_Version::supports_avx512dq());
predicate(VM_Version::supports_avx512dq() &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVL src (LoadVector mem)));
format %{ "vpmullq $dst,$src,$mem\t! mul packedL" %}
ins_encode %{
Expand Down Expand Up @@ -5503,7 +5518,8 @@ instruct vmulF_reg(vec dst, vec src1, vec src2) %{
%}

instruct vmulF_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVF src (LoadVector mem)));
format %{ "vmulps $dst,$src,$mem\t! mul packedF" %}
ins_encode %{
Expand Down Expand Up @@ -5536,7 +5552,8 @@ instruct vmulD_reg(vec dst, vec src1, vec src2) %{
%}

instruct vmulD_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (MulVD src (LoadVector mem)));
format %{ "vmulpd $dst,$src,$mem\t! mul packedD" %}
ins_encode %{
Expand Down Expand Up @@ -5607,7 +5624,8 @@ instruct vdivF_reg(vec dst, vec src1, vec src2) %{
%}

instruct vdivF_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (DivVF src (LoadVector mem)));
format %{ "vdivps $dst,$src,$mem\t! div packedF" %}
ins_encode %{
Expand Down Expand Up @@ -5640,7 +5658,8 @@ instruct vdivD_reg(vec dst, vec src1, vec src2) %{
%}

instruct vdivD_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (DivVD src (LoadVector mem)));
format %{ "vdivpd $dst,$src,$mem\t! div packedD" %}
ins_encode %{
Expand Down Expand Up @@ -5824,6 +5843,7 @@ instruct vsqrtF_reg(vec dst, vec src) %{
%}

instruct vsqrtF_mem(vec dst, memory mem) %{
predicate(vector_length_in_bytes(n->in(1)) > 8);
match(Set dst (SqrtVF (LoadVector mem)));
format %{ "vsqrtps $dst,$mem\t! sqrt packedF" %}
ins_encode %{
Expand All @@ -5847,6 +5867,7 @@ instruct vsqrtD_reg(vec dst, vec src) %{
%}

instruct vsqrtD_mem(vec dst, memory mem) %{
predicate(vector_length_in_bytes(n->in(1)) > 8);
match(Set dst (SqrtVD (LoadVector mem)));
format %{ "vsqrtpd $dst,$mem\t! sqrt packedD" %}
ins_encode %{
Expand Down Expand Up @@ -6459,7 +6480,8 @@ instruct vand_reg(vec dst, vec src1, vec src2) %{
%}

instruct vand_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (AndV src (LoadVector mem)));
format %{ "vpand $dst,$src,$mem\t! and vectors" %}
ins_encode %{
Expand Down Expand Up @@ -6493,7 +6515,8 @@ instruct vor_reg(vec dst, vec src1, vec src2) %{
%}

instruct vor_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (OrV src (LoadVector mem)));
format %{ "vpor $dst,$src,$mem\t! or vectors" %}
ins_encode %{
Expand Down Expand Up @@ -6527,7 +6550,8 @@ instruct vxor_reg(vec dst, vec src1, vec src2) %{
%}

instruct vxor_mem(vec dst, vec src, memory mem) %{
predicate(UseAVX > 0);
predicate((UseAVX > 0) &&
(vector_length_in_bytes(n->in(1)) > 8));
match(Set dst (XorV src (LoadVector mem)));
format %{ "vpxor $dst,$src,$mem\t! xor vectors" %}
ins_encode %{
Expand Down Expand Up @@ -7947,6 +7971,7 @@ instruct vfmaF_reg(vec a, vec b, vec c) %{
%}

instruct vfmaF_mem(vec a, memory b, vec c) %{
predicate(vector_length_in_bytes(n->in(1)) > 8);
match(Set c (FmaVF c (Binary a (LoadVector b))));
format %{ "fmaps $a,$b,$c\t# $c = $a * $b + $c fma packedF" %}
ins_cost(150);
Expand All @@ -7971,6 +7996,7 @@ instruct vfmaD_reg(vec a, vec b, vec c) %{
%}

instruct vfmaD_mem(vec a, memory b, vec c) %{
predicate(vector_length_in_bytes(n->in(1)) > 8);
match(Set c (FmaVD c (Binary a (LoadVector b))));
format %{ "fmapd $a,$b,$c\t# $c = $a * $b + $c fma packedD" %}
ins_cost(150);
Expand Down Expand Up @@ -8048,6 +8074,7 @@ instruct vpternlog(vec dst, vec src2, vec src3, immU8 func) %{
%}

instruct vpternlog_mem(vec dst, vec src2, memory src3, immU8 func) %{
predicate(vector_length_in_bytes(n->in(1)) > 8);
match(Set dst (MacroLogicV (Binary dst src2) (Binary (LoadVector src3) func)));
effect(TEMP dst);
format %{ "vpternlogd $dst,$src2,$src3,$func\t! vector ternary logic" %}
Expand Down

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