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8288445: AArch64: C2 compilation fails with guarantee(!true || (true …
…&& (shift != 0))) failed: impossible encoding

Reviewed-by: phh
Backport-of: b4490386fe348250e88347526172c1c27ef01eba
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yftsai authored and Paul Hohensee committed Sep 6, 2022
1 parent c4721bc commit 328ea9d
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Showing 4 changed files with 115 additions and 32 deletions.
10 changes: 10 additions & 0 deletions src/hotspot/cpu/aarch64/aarch64.ad
Expand Up @@ -4295,6 +4295,16 @@ operand immI_65535()
interface(CONST_INTER);
%}

operand immI_positive()
%{
predicate(n->get_int() > 0);
match(ConI);

op_cost(0);
format %{ %}
interface(CONST_INTER);
%}

operand immL_255()
%{
predicate(n->get_long() == 255L);
Expand Down
56 changes: 28 additions & 28 deletions src/hotspot/cpu/aarch64/aarch64_neon.ad
Expand Up @@ -4428,7 +4428,7 @@ instruct vsll16B_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
instruct vsra8B_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
match(Set dst (RShiftVB src (RShiftCntV shift)));
Expand All @@ -4443,7 +4443,7 @@ instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
instruct vsra16B_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (RShiftVB src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4457,7 +4457,7 @@ instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
instruct vsrl8B_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8);
match(Set dst (URShiftVB src (RShiftCntV shift)));
Expand All @@ -4477,7 +4477,7 @@ instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl16B_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (URShiftVB src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand Down Expand Up @@ -4632,7 +4632,7 @@ instruct vsll8S_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
instruct vsra4S_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (RShiftVS src (RShiftCntV shift)));
Expand All @@ -4647,7 +4647,7 @@ instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
instruct vsra8S_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (RShiftVS src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4661,7 +4661,7 @@ instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
instruct vsrl4S_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2 ||
n->as_Vector()->length() == 4);
match(Set dst (URShiftVS src (RShiftCntV shift)));
Expand All @@ -4681,7 +4681,7 @@ instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl8S_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (URShiftVS src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand Down Expand Up @@ -4820,7 +4820,7 @@ instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
instruct vsra2I_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (RShiftVI src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4833,7 +4833,7 @@ instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
instruct vsra4I_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (RShiftVI src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4846,7 +4846,7 @@ instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
instruct vsrl2I_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (URShiftVI src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4859,7 +4859,7 @@ instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl4I_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (URShiftVI src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand Down Expand Up @@ -4932,7 +4932,7 @@ instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
instruct vsra2L_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (RShiftVL src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4945,7 +4945,7 @@ instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
instruct vsrl2L_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (URShiftVL src (RShiftCntV shift)));
ins_cost(INSN_COST);
Expand All @@ -4958,7 +4958,7 @@ instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsraa8B_imm(vecD dst, vecD src, immI shift) %{
instruct vsraa8B_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (AddVB dst (RShiftVB src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -4972,7 +4972,7 @@ instruct vsraa8B_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsraa16B_imm(vecX dst, vecX src, immI shift) %{
instruct vsraa16B_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (AddVB dst (RShiftVB src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -4986,7 +4986,7 @@ instruct vsraa16B_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsraa4S_imm(vecD dst, vecD src, immI shift) %{
instruct vsraa4S_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (AddVS dst (RShiftVS src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5000,7 +5000,7 @@ instruct vsraa4S_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsraa8S_imm(vecX dst, vecX src, immI shift) %{
instruct vsraa8S_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (AddVS dst (RShiftVS src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5014,7 +5014,7 @@ instruct vsraa8S_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsraa2I_imm(vecD dst, vecD src, immI shift) %{
instruct vsraa2I_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (AddVI dst (RShiftVI src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5027,7 +5027,7 @@ instruct vsraa2I_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsraa4I_imm(vecX dst, vecX src, immI shift) %{
instruct vsraa4I_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (AddVI dst (RShiftVI src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5040,7 +5040,7 @@ instruct vsraa4I_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsraa2L_imm(vecX dst, vecX src, immI shift) %{
instruct vsraa2L_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (AddVL dst (RShiftVL src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5053,7 +5053,7 @@ instruct vsraa2L_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrla8B_imm(vecD dst, vecD src, immI shift) %{
instruct vsrla8B_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (AddVB dst (URShiftVB src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5068,7 +5068,7 @@ instruct vsrla8B_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrla16B_imm(vecX dst, vecX src, immI shift) %{
instruct vsrla16B_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 16);
match(Set dst (AddVB dst (URShiftVB src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5083,7 +5083,7 @@ instruct vsrla16B_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
instruct vsrla4S_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (AddVS dst (URShiftVS src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5098,7 +5098,7 @@ instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrla8S_imm(vecX dst, vecX src, immI shift) %{
instruct vsrla8S_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 8);
match(Set dst (AddVS dst (URShiftVS src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5113,7 +5113,7 @@ instruct vsrla8S_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrla2I_imm(vecD dst, vecD src, immI shift) %{
instruct vsrla2I_imm(vecD dst, vecD src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (AddVI dst (URShiftVI src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5126,7 +5126,7 @@ instruct vsrla2I_imm(vecD dst, vecD src, immI shift) %{
ins_pipe(vshift64_imm);
%}

instruct vsrla4I_imm(vecX dst, vecX src, immI shift) %{
instruct vsrla4I_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 4);
match(Set dst (AddVI dst (URShiftVI src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -5139,7 +5139,7 @@ instruct vsrla4I_imm(vecX dst, vecX src, immI shift) %{
ins_pipe(vshift128_imm);
%}

instruct vsrla2L_imm(vecX dst, vecX src, immI shift) %{
instruct vsrla2L_imm(vecX dst, vecX src, immI_positive shift) %{
predicate(n->as_Vector()->length() == 2);
match(Set dst (AddVL dst (URShiftVL src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
Expand Up @@ -1992,7 +1992,7 @@ instruct vsll$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
%}')dnl
define(`VSRA_IMM', `
instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
',
$3$4, 4S, n->as_Vector()->length() == 2 ||`
Expand All @@ -2017,7 +2017,7 @@ instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
%}')dnl
dnl
define(`VSRL_IMM', `
instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
',
$3$4, 4S, n->as_Vector()->length() == 2 ||`
Expand Down Expand Up @@ -2052,7 +2052,7 @@ instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
%}')dnl
dnl
define(`VSRLA_IMM', `
instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
predicate(n->as_Vector()->length() == $3);
match(Set dst (AddV$4 dst (URShiftV$4 src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand All @@ -2076,7 +2076,7 @@ instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
%}')dnl
dnl
define(`VSRAA_IMM', `
instruct vsraa$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
instruct vsraa$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
predicate(n->as_Vector()->length() == $3);
match(Set dst (AddV$4 dst (RShiftV$4 src (RShiftCntV shift))));
ins_cost(INSN_COST);
Expand Down
73 changes: 73 additions & 0 deletions test/hotspot/jtreg/compiler/codegen/ShiftByZero.java
@@ -0,0 +1,73 @@
/*
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/

/*
* @test
* @bug 8288445
* @summary Test shift by 0
* @run main/othervm -Xbatch -XX:-TieredCompilation
* compiler.codegen.ShiftByZero
*/

package compiler.codegen;

public class ShiftByZero {

public static final int N = 64;

public static int[] i32 = new int[N];

public static void bMeth() {
int shift = i32[0];
// This loop is to confuse the optimizer, so that "shift" is
// optimized to 0 only after loop vectorization.
for (int i8 = 279; i8 > 1; --i8) {
shift <<= 6;
}
// low 6 bits of shift are 0, so shift can be
// simplified to constant 0
{
for (int i = 0; i < N; ++i) {
i32[i] += i32[i] >>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] += i32[i] >>>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] >>>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] >>= shift;
}
for (int i = 0; i < N; ++i) {
i32[i] <<= shift;
}
}
}

public static void main(String[] strArr) {
for (int i = 0; i < 20_000; i++) {
bMeth();
}
}
}

3 comments on commit 328ea9d

@openjdk-notifier
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@earthling-amzn
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/backport jdk11u-dev

@openjdk
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@openjdk openjdk bot commented on 328ea9d Oct 13, 2022

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@earthling-amzn Could not automatically backport 328ea9d0 to openjdk/jdk11u-dev due to conflicts in the following files:

  • src/hotspot/cpu/aarch64/aarch64_neon.ad
  • src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

Please fetch the appropriate branch/commit and manually resolve these conflicts by using the following commands in your personal fork of openjdk/jdk11u-dev. Note: these commands are just some suggestions and you can use other equivalent commands you know.

# Fetch the up-to-date version of the target branch
$ git fetch --no-tags https://git.openjdk.org/jdk11u-dev master:master

# Check out the target branch and create your own branch to backport
$ git checkout master
$ git checkout -b earthling-amzn-backport-328ea9d0

# Fetch the commit you want to backport
$ git fetch --no-tags https://git.openjdk.org/jdk17u-dev 328ea9d0ff13a2b3f8c539589aa13178c2f50007

# Backport the commit
$ git cherry-pick --no-commit 328ea9d0ff13a2b3f8c539589aa13178c2f50007
# Resolve conflicts now

# Commit the files you have modified
$ git add files/with/resolved/conflicts
$ git commit -m 'Backport 328ea9d0ff13a2b3f8c539589aa13178c2f50007'

Once you have resolved the conflicts as explained above continue with creating a pull request towards the openjdk/jdk11u-dev with the title Backport 328ea9d0ff13a2b3f8c539589aa13178c2f50007.

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