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8276799: Implementation of JEP 422: Linux/RISC-V Port
8282306: os::is_first_C_frame(frame*) crashes on invalid link access 8282477: [x86, aarch64] vmassert(_last_Java_pc == NULL, "already walkable"); fails with async profiler 8283865: riscv: Break down -XX:+UseRVB into seperate options for each bitmanip extension 8284068: riscv: should call Atomic::release_store in JavaThread::set_thread_state 8284937: riscv: should not allocate special register for temp 8285303: riscv: Incorrect register mask in call_native_base 8287418: riscv: Fix correctness issue of MacroAssembler::movptr 8297644: RISC-V: Compilation error when shenandoah is disabled 8291952: riscv: Remove PRAGMA_NONNULL_IGNORED 8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops* 8285699: riscv: Provide information when hitting a HaltNode 8285711: riscv: RVC: Support disassembler show-bytes option 8287425: Remove unnecessary register push for MacroAssembler::check_klass_subtype_slow_path 8287552: riscv: Fix comment typo in li64 8287970: riscv: jdk/incubator/vector/*VectorTests failing 8290137: riscv: small refactoring for add_memory_int32/64 8290164: compiler/runtime/TestConstantsInError.java fails on riscv 8290496: riscv: Fix build warnings-as-errors with GCC 11 8291893: riscv: remove fence.i used in user space 8291947: riscv: fail to build after JDK-8290840 8292867: RISC-V: Simplify weak CAS return value handling 8293050: RISC-V: Remove redundant non-null assertions about macro-assembler 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub 8293474: RISC-V: Unify the way of moving function pointer 8293524: RISC-V: Use macro-assembler functions as appropriate 8293566: RISC-V: Clean up push and pop registers 8294012: RISC-V: get/put_native_u8 missing the case when address&7 is 6 8294083: RISC-V: Minimal build failed with --disable-precompiled-headers 8294086: RISC-V: Cleanup InstructionMark usages in the backend 8294087: RISC-V: RVC: Fix a potential alignment issue and add more alignment assertions for the patchable calls/nops 8294187: RISC-V: Unify all relocations for the backend into AbstractAssembler::relocate() 8294366: RISC-V: Partially mark out incompressible regions 8294430: RISC-V: Small refactoring for movptr_with_offset 8294492: RISC-V: Use li instead of patchable movptr at non-patchable callsites 8294679: RISC-V: Misc crash dump improvements 8295110: RISC-V: Mark out relocations as incompressible 8295270: RISC-V: Clean up and refactoring for assembler functions 8295396: RISC-V: Cleanup useless CompressibleRegions 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic 8295968: RISC-V: Rename some assembler intrinsic functions for RVV 1.0 8296435: RISC-V: Small refactoring for increment/decrement 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec 8296448: RISC-V: Fix temp usages of heapbase register killed by MacroAssembler::en/decode_klass_not_null 8296602: RISC-V: improve performance of copy_memory stub 8296771: RISC-V: C2: assert(false) failed: bad AD file 8296916: RISC-V: Move some small macro-assembler functions to header file 8297359: RISC-V: improve performance of floating Max Min intrinsics 8297697: RISC-V: Add support for SATP mode detection 8301067: RISC-V: better error message when reporting unsupported satp modes 8297715: RISC-V: C2: Use single-bit instructions from the Zbs extension 8299168: RISC-V: Fix MachNode size mismatch for MacroAssembler::_verify_oops* 8299847: RISC-V: Improve PrintOptoAssembly output of CMoveI/L nodes 8300109: RISC-V: Improve code generation for MinI/MaxI nodes 8301033: RISC-V: Handle special cases for MinI/MaxI nodes for Zbb 8301036: RISC-V: Factor out functions baseOffset & baseOffset32 from MacroAssembler 8301153: RISC-V: pipeline class for several instructions is not set correctly 8301313: RISC-V: C2: assert(false) failed: bad AD file due to missing match rule 8301628: RISC-V: c2 fix pipeline class for several instructions 8301818: RISC-V: Factor out function mvw from MacroAssembler 8302114: RISC-V: Several foreign jtreg tests fail with debug build after JDK-8301818 8301852: RISC-V: Optimize class atomic when order is memory_order_relaxed 8302289: RISC-V: Use bgez instruction in arraycopy_simple_check when possible 8302776: RISC-V: Fix typo CSR_INSTERT to CSR_INSTRET 8304293: RISC-V: JDK-8276799 missed atomic intrinsic support for C1 8305006: Use correct register in riscv_enc_fast_unlock() 8305008: RISC-V: Factor out immediate checking functions from assembler_riscv.inline.hpp 8305112: RISC-V: Typo fix for RVC description 8305512: RISC-V: Enable RVC extension by default on supported hardware 8305728: RISC-V: Use bexti instruction to do single-bit testing 8306667: RISC-V: Fix storeImmN0 matching rule by using zr register 8307150: RISC-V: Remove remaining StoreLoad barrier with UseCondCardMark for Serial/Parallel GC 8307446: RISC-V: Improve performance of floating point to integer conversion 8307651: RISC-V: stringL_indexof_char instruction has wrong format string 8308089: [riscv-port-jdk17u] Intrinsify Unsafe.storeStoreFence 8308277: RISC-V: Improve vectorization of Match.sqrt() on floats 8308997: RISC-V: Sign extend when comparing 32-bit value with zero instead of testing the sign bit 8309427: [riscv-port-jdk17u] Remove unused RoundDoubleModeV C2 node 8305236: Some LoadLoad barriers in the interpreter are unnecessary after JDK-8220051 8285630: Fix a configure error in RISC-V cross build 8277417: C1 LIR instruction for load-klass Reviewed-by: vkempik, goetz, shade, yadongwang, fjiang, luhenry Backport-of: 5905b02c0e2643ae8d097562f181953f6c88fc89
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