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8307423: [s390x] Represent Registers as values
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Reviewed-by: lucy
Backport-of: 8bbd264c6e4b4045a218f11ae6b5b4f395bc2aa9
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offamitkumar authored and TheRealMDoerr committed May 13, 2024
1 parent bf4b15c commit f789e38
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Showing 10 changed files with 257 additions and 435 deletions.
5 changes: 0 additions & 5 deletions src/hotspot/cpu/s390/assembler_s390.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -189,11 +189,6 @@ class Address {
_index(noreg),
_disp(0) {}

Address(Register base, Register index, intptr_t disp = 0) :
_base(base),
_index(index),
_disp(disp) {}

Address(Register base, intptr_t disp = 0) :
_base(base),
_index(noreg),
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -869,13 +869,13 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
// 4-byte accesses only! Don't use it to access 8 bytes!
Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
ShouldNotCallThis();
return 0; // unused
return Address(); // unused
}

// 4-byte accesses only! Don't use it to access 8 bytes!
Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
ShouldNotCallThis();
return 0; // unused
return Address(); // unused
}

void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
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8 changes: 4 additions & 4 deletions src/hotspot/cpu/s390/interpreterRT_s390.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016 SAP SE. All rights reserved.
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -73,7 +73,7 @@ InterpreterRuntime::SignatureHandlerGenerator::SignatureHandlerGenerator(
void InterpreterRuntime::SignatureHandlerGenerator::pass_int() {
int int_arg_nr = jni_offset() - _fp_arg_nr;
Register r = (int_arg_nr < 5 /*max_int_register_arguments*/) ?
as_Register(int_arg_nr) + Z_ARG1->encoding() : Z_R0;
as_Register(int_arg_nr + Z_ARG1->encoding()) : Z_R0;

__ z_lgf(r, locals_j_arg_at(offset()));
if (DEBUG_ONLY(true ||) int_arg_nr >= 5) {
Expand All @@ -84,7 +84,7 @@ void InterpreterRuntime::SignatureHandlerGenerator::pass_int() {
void InterpreterRuntime::SignatureHandlerGenerator::pass_long() {
int int_arg_nr = jni_offset() - _fp_arg_nr;
Register r = (int_arg_nr < 5 /*max_int_register_arguments*/) ?
as_Register(int_arg_nr) + Z_ARG1->encoding() : Z_R0;
as_Register(int_arg_nr + Z_ARG1->encoding()) : Z_R0;

__ z_lg(r, locals_j_arg_at(offset() + 1)); // Long resides in upper slot.
if (DEBUG_ONLY(true ||) int_arg_nr >= 5) {
Expand Down Expand Up @@ -115,7 +115,7 @@ void InterpreterRuntime::SignatureHandlerGenerator::pass_double() {
void InterpreterRuntime::SignatureHandlerGenerator::pass_object() {
int int_arg_nr = jni_offset() - _fp_arg_nr;
Register r = (int_arg_nr < 5 /*max_int_register_arguments*/) ?
as_Register(int_arg_nr) + Z_ARG1->encoding() : Z_R0;
as_Register(int_arg_nr + Z_ARG1->encoding()) : Z_R0;

// The handle for a receiver will never be null.
bool do_NULL_check = offset() != 0 || is_static();
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/s390/methodHandles_s390.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -634,7 +634,7 @@ void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adapt
if (!log_is_enabled(Info, methodhandles)) { return; }

// If arg registers are contiguous, we can use STMG/LMG.
assert((Z_ARG5->encoding() - Z_ARG1->encoding() + 1) == RegisterImpl::number_of_arg_registers, "Oops");
assert((Z_ARG5->encoding() - Z_ARG1->encoding() + 1) == Register::number_of_arg_registers, "Oops");

BLOCK_COMMENT("trace_method_handle {");

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39 changes: 0 additions & 39 deletions src/hotspot/cpu/s390/register_definitions_s390.cpp

This file was deleted.

18 changes: 9 additions & 9 deletions src/hotspot/cpu/s390/register_s390.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2017 SAP SE. All rights reserved.
* Copyright (c) 2016, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2016, 2023 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand All @@ -27,27 +27,27 @@
#include "register_s390.hpp"


const int ConcreteRegisterImpl::max_gpr = RegisterImpl::number_of_registers * 2;
const int ConcreteRegisterImpl::max_gpr = Register::number_of_registers * 2;
const int ConcreteRegisterImpl::max_fpr = ConcreteRegisterImpl::max_gpr +
FloatRegisterImpl::number_of_registers * 2;
FloatRegister::number_of_registers * 2;

const char* RegisterImpl::name() const {
const char* Register::name() const {
const char* names[number_of_registers] = {
"Z_R0", "Z_R1", "Z_R2", "Z_R3", "Z_R4", "Z_R5", "Z_R6", "Z_R7",
"Z_R8", "Z_R9", "Z_R10", "Z_R11", "Z_R12", "Z_R13", "Z_R14", "Z_R15"
};
return is_valid() ? names[encoding()] : "noreg";
}

const char* FloatRegisterImpl::name() const {
const char* FloatRegister::name() const {
const char* names[number_of_registers] = {
"Z_F0", "Z_F1", "Z_F2", "Z_F3", "Z_F4", "Z_F5", "Z_F6", "Z_F7", "Z_F8", "Z_F9",
"Z_F10", "Z_F11", "Z_F12", "Z_F13", "Z_F14", "Z_F15"
"Z_F0", "Z_F1", "Z_F2", "Z_F3", "Z_F4", "Z_F5", "Z_F6", "Z_F7",
"Z_F8", "Z_F9", "Z_F10", "Z_F11", "Z_F12", "Z_F13", "Z_F14", "Z_F15"
};
return is_valid() ? names[encoding()] : "fnoreg";
}

const char* VectorRegisterImpl::name() const {
const char* VectorRegister::name() const {
const char* names[number_of_registers] = {
"Z_V0", "Z_V1", "Z_V2", "Z_V3", "Z_V4", "Z_V5", "Z_V6", "Z_V7",
"Z_V8", "Z_V9", "Z_V10", "Z_V11", "Z_V12", "Z_V13", "Z_V14", "Z_V15",
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