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8278508: Enable X86 maskAll instruction pattern for 32 bit JVM.
Reviewed-by: kvn, sviswanathan
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Jatin Bhateja committed Dec 22, 2021
1 parent 9ee3ccf commit 97c5cd7facf1d3565038c078d5688c7da15ad14e
Showing 10 changed files with 119 additions and 56 deletions.
@@ -2788,6 +2788,15 @@ void Assembler::kshiftlbl(KRegister dst, KRegister src, int imm8) {
emit_int8(imm8);
}

void Assembler::kshiftlql(KRegister dst, KRegister src, int imm8) {
assert(VM_Version::supports_avx512bw(), "");
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
emit_int16(0x33, (0xC0 | encode));
emit_int8(imm8);
}


void Assembler::kshiftrbl(KRegister dst, KRegister src, int imm8) {
assert(VM_Version::supports_avx512dq(), "");
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -2819,6 +2828,13 @@ void Assembler::kshiftrql(KRegister dst, KRegister src, int imm8) {
emit_int8(imm8);
}

void Assembler::kunpckdql(KRegister dst, KRegister src1, KRegister src2) {
assert(VM_Version::supports_avx512bw(), "");
InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
emit_int16(0x4B, (0xC0 | encode));
}

void Assembler::movb(Address dst, int imm8) {
InstructionMark im(this);
prefix(dst);
@@ -1510,12 +1510,15 @@ class Assembler : public AbstractAssembler {

void kxnorbl(KRegister dst, KRegister src1, KRegister src2);
void kshiftlbl(KRegister dst, KRegister src, int imm8);
void kshiftlql(KRegister dst, KRegister src, int imm8);
void kshiftrbl(KRegister dst, KRegister src, int imm8);
void kshiftrwl(KRegister dst, KRegister src, int imm8);
void kshiftrdl(KRegister dst, KRegister src, int imm8);
void kshiftrql(KRegister dst, KRegister src, int imm8);
void ktestq(KRegister src1, KRegister src2);
void ktestd(KRegister src1, KRegister src2);
void kunpckdql(KRegister dst, KRegister src1, KRegister src2);


void ktestql(KRegister dst, KRegister src);
void ktestdl(KRegister dst, KRegister src);
@@ -4273,3 +4273,30 @@ void C2_MacroAssembler::vector_mask_operation(int opc, Register dst, XMMRegister
vector_mask_operation_helper(opc, dst, tmp, masklen);
}
#endif

void C2_MacroAssembler::vector_maskall_operation(KRegister dst, Register src, int mask_len) {
if (VM_Version::supports_avx512bw()) {
if (mask_len > 32) {
kmovql(dst, src);
} else {
kmovdl(dst, src);
if (mask_len != 32) {
kshiftrdl(dst, dst, 32 - mask_len);
}
}
} else {
assert(mask_len <= 16, "");
kmovwl(dst, src);
if (mask_len != 16) {
kshiftrwl(dst, dst, 16 - mask_len);
}
}
}

#ifndef _LP64
void C2_MacroAssembler::vector_maskall_operation32(KRegister dst, Register src, KRegister tmp, int mask_len) {
assert(VM_Version::supports_avx512bw(), "");
kmovdl(tmp, src);
kunpckdql(dst, tmp, tmp);
}
#endif
@@ -231,6 +231,13 @@
void vector_mask_operation(int opc, Register dst, XMMRegister mask, XMMRegister xtmp,
Register tmp, int masklen, BasicType bt, int vec_enc);
#endif

void vector_maskall_operation(KRegister dst, Register src, int mask_len);

#ifndef _LP64
void vector_maskall_operation32(KRegister dst, Register src, KRegister ktmp, int mask_len);
#endif

void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);

@@ -1827,7 +1827,7 @@ const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType
}
break;
case Op_MaskAll:
if (!is_LP64 || !VM_Version::supports_evex()) {
if (!VM_Version::supports_evex()) {
return false;
}
if ((vlen > 16 || is_subword_type(bt)) && !VM_Version::supports_avx512bw()) {
@@ -9452,64 +9452,18 @@ instruct evcmp_masked(kReg dst, vec src1, vec src2, immI8 cond, kReg mask, rRegP
ins_pipe( pipe_slow );
%}

#ifdef _LP64
instruct mask_all_evexI_imm(kReg dst, immI cnt, rRegL tmp) %{
match(Set dst (MaskAll cnt));
effect(TEMP_DEF dst, TEMP tmp);
format %{ "mask_all_evexI $dst, $cnt \t! using $tmp as TEMP" %}
ins_encode %{
int vec_len = Matcher::vector_length(this);
if (VM_Version::supports_avx512bw()) {
__ movq($tmp$$Register, $cnt$$constant);
__ kmovql($dst$$KRegister, $tmp$$Register);
__ kshiftrql($dst$$KRegister, $dst$$KRegister, 64 - vec_len);
} else {
assert(vec_len <= 16, "");
__ movq($tmp$$Register, $cnt$$constant);
__ kmovwl($dst$$KRegister, $tmp$$Register);
__ kshiftrwl($dst$$KRegister, $dst$$KRegister, 16 - vec_len);
}
%}
ins_pipe( pipe_slow );
%}

instruct mask_all_evexI(kReg dst, rRegI src, rRegL tmp) %{
match(Set dst (MaskAll src));
effect(TEMP_DEF dst, TEMP tmp);
format %{ "mask_all_evexI $dst, $src \t! using $tmp as TEMP" %}
ins_encode %{
int vec_len = Matcher::vector_length(this);
if (VM_Version::supports_avx512bw()) {
__ movslq($tmp$$Register, $src$$Register);
__ kmovql($dst$$KRegister, $tmp$$Register);
__ kshiftrql($dst$$KRegister, $dst$$KRegister, 64 - vec_len);
} else {
assert(vec_len <= 16, "");
__ kmovwl($dst$$KRegister, $src$$Register);
__ kshiftrwl($dst$$KRegister, $dst$$KRegister, 16 - vec_len);
}
%}
ins_pipe( pipe_slow );
%}

instruct mask_all_evexL(kReg dst, rRegL src) %{
instruct mask_all_evexI_LE32(kReg dst, rRegI src) %{
predicate(Matcher::vector_length(n) <= 32);
match(Set dst (MaskAll src));
effect(TEMP_DEF dst);
format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
format %{ "mask_all_evexI_LE32 $dst, $src \t" %}
ins_encode %{
int vec_len = Matcher::vector_length(this);
if (VM_Version::supports_avx512bw()) {
__ kmovql($dst$$KRegister, $src$$Register);
__ kshiftrql($dst$$KRegister, $dst$$KRegister, 64 - vec_len);
} else {
assert(vec_len <= 16, "");
__ kmovwl($dst$$KRegister, $src$$Register);
__ kshiftrwl($dst$$KRegister, $dst$$KRegister, 16 - vec_len);
}
int mask_len = Matcher::vector_length(this);
__ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
%}
ins_pipe( pipe_slow );
%}

#ifdef _LP64
instruct mask_not_immLT8(kReg dst, kReg src, rRegI rtmp, kReg ktmp, immI_M1 cnt) %{
predicate(Matcher::vector_length(n) < 8 && VM_Version::supports_avx512dq());
match(Set dst (XorVMask src (MaskAll cnt)));
@@ -13847,7 +13847,40 @@ instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
ins_pipe(pipe_slow);
%}

instruct mask_all_evexL_LT32(kReg dst, eRegL src) %{
predicate(Matcher::vector_length(n) <= 32);
match(Set dst (MaskAll src));
format %{ "mask_all_evexL_LE32 $dst, $src \t" %}
ins_encode %{
int mask_len = Matcher::vector_length(this);
__ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
%}
ins_pipe( pipe_slow );
%}

instruct mask_all_evexL_GT32(kReg dst, eRegL src, kReg ktmp) %{
predicate(Matcher::vector_length(n) > 32);
match(Set dst (MaskAll src));
effect(TEMP ktmp);
format %{ "mask_all_evexL_GT32 $dst, $src \t! using $ktmp as TEMP " %}
ins_encode %{
int mask_len = Matcher::vector_length(this);
__ vector_maskall_operation32($dst$$KRegister, $src$$Register, $ktmp$$KRegister, mask_len);
%}
ins_pipe( pipe_slow );
%}

instruct mask_all_evexI_GT32(kReg dst, rRegI src, kReg ktmp) %{
predicate(Matcher::vector_length(n) > 32);
match(Set dst (MaskAll src));
effect(TEMP ktmp);
format %{ "mask_all_evexI_GT32 $dst, $src \t! using $ktmp as TEMP" %}
ins_encode %{
int mask_len = Matcher::vector_length(this);
__ vector_maskall_operation32($dst$$KRegister, $src$$Register, $ktmp$$KRegister, mask_len);
%}
ins_pipe( pipe_slow );
%}

// ============================================================================
// Safepoint Instruction
@@ -13011,6 +13011,29 @@ instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
ins_pipe(ialu_reg_mem);
%}

instruct mask_all_evexL(kReg dst, rRegL src) %{
match(Set dst (MaskAll src));
format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
ins_encode %{
int mask_len = Matcher::vector_length(this);
__ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
%}
ins_pipe( pipe_slow );
%}

instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
predicate(Matcher::vector_length(n) > 32);
match(Set dst (MaskAll src));
effect(TEMP tmp);
format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
ins_encode %{
int mask_len = Matcher::vector_length(this);
__ movslq($tmp$$Register, $src$$Register);
__ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
%}
ins_pipe( pipe_slow );
%}

// ============================================================================
// Procedure Call/Return Instructions
// Call Java Static Instruction
@@ -24,7 +24,7 @@
/*
* @test
* @modules jdk.incubator.vector
* @run testng/othervm -ea -esa -Xbatch -XX:-TieredCompilation Byte512VectorTests
* @run testng/othervm/timeout=240 -ea -esa -Xbatch -XX:-TieredCompilation Byte512VectorTests
*/

// -- This file was mechanically generated: Do not edit! -- //
@@ -24,7 +24,7 @@
/*
* @test
* @modules jdk.incubator.vector
* @run testng/othervm -ea -esa -Xbatch -XX:-TieredCompilation ByteMaxVectorTests
* @run testng/othervm/timeout=240 -ea -esa -Xbatch -XX:-TieredCompilation ByteMaxVectorTests
*/

// -- This file was mechanically generated: Do not edit! -- //
@@ -39,7 +39,7 @@
* @test
* @modules jdk.incubator.vector
* @modules java.base/jdk.internal.vm.annotation
* @run testng/othervm --add-opens jdk.incubator.vector/jdk.incubator.vector=ALL-UNNAMED
* @run testng/othervm/timeout=240 --add-opens jdk.incubator.vector/jdk.incubator.vector=ALL-UNNAMED
* -XX:-TieredCompilation VectorReshapeTests
*/

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