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8324824: AArch64: Detect Ampere-1B core and update default options fo…
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…r Ampere CPUs

Backport-of: 9936aeea32b71509151099e6d28905e0322b2bc2
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Patrick Zhang authored and shipilev committed Mar 1, 2024
1 parent e667521 commit 4243aed
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Showing 2 changed files with 12 additions and 3 deletions.
12 changes: 10 additions & 2 deletions src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -144,11 +144,19 @@ void VM_Version::initialize() {
}
}

// Ampere CPUs: Ampere-1 and Ampere-1A
if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) || (_model == CPU_MODEL_AMPERE_1A))) {
// Ampere CPUs
if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) ||
(_model == CPU_MODEL_AMPERE_1A) ||
(_model == CPU_MODEL_AMPERE_1B))) {
if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
}
if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
}
if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
}
}

// ThunderX
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3 changes: 2 additions & 1 deletion src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,8 @@ enum Ampere_CPU_Model {
CPU_MODEL_ALTRA = 0xd0c, /* CPU implementer is CPU_ARM, Neoverse N1 */
CPU_MODEL_ALTRAMAX = 0xd0c, /* CPU implementer is CPU_ARM, Neoverse N1 */
CPU_MODEL_AMPERE_1 = 0xac3, /* CPU implementer is CPU_AMPERE */
CPU_MODEL_AMPERE_1A = 0xac4 /* CPU implementer is CPU_AMPERE */
CPU_MODEL_AMPERE_1A = 0xac4, /* CPU implementer is CPU_AMPERE */
CPU_MODEL_AMPERE_1B = 0xac5 /* AMPERE_1B core Implements ARMv8.7 with CSSC, MTE, SM3/SM4 extensions */
};

#define CPU_FEATURE_FLAGS(decl) \
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