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zifeihanRealFYang
zifeihan
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RealFYang
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8330094: RISC-V: Save and restore FRM in the call stub
Reviewed-by: fyang Backport-of: b0496096dc8d7dc7acf28aa006141a3ecea446de
1 parent 3bb8eee commit 835d016

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3 files changed

+25
-13
lines changed

3 files changed

+25
-13
lines changed

‎src/hotspot/cpu/riscv/frame_riscv.hpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
// Entry frames
132132
// n.b. these values are determined by the layout defined in
133133
// stubGenerator for the Java call stub
134-
entry_frame_after_call_words = 34,
134+
entry_frame_after_call_words = 35,
135135
entry_frame_call_wrapper_offset = -10,
136136

137137
// we don't need a save area

‎src/hotspot/cpu/riscv/riscv_v.ad

-9
Original file line numberDiff line numberDiff line change
@@ -2942,7 +2942,6 @@ instruct vloadcon(vReg dst, immI0 src) %{
29422942
__ vsetvli_helper(bt, Matcher::vector_length(this));
29432943
__ vid_v(as_VectorRegister($dst$$reg));
29442944
if (is_floating_point_type(bt)) {
2945-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
29462945
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg));
29472946
}
29482947
%}
@@ -3156,7 +3155,6 @@ instruct vcvtBtoX(vReg dst, vReg src) %{
31563155
if (is_floating_point_type(bt)) {
31573156
__ integer_extend_v(as_VectorRegister($dst$$reg), bt == T_FLOAT ? T_INT : T_LONG,
31583157
Matcher::vector_length(this), as_VectorRegister($src$$reg), T_BYTE);
3159-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
31603158
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg));
31613159
} else {
31623160
__ integer_extend_v(as_VectorRegister($dst$$reg), bt,
@@ -3203,7 +3201,6 @@ instruct vcvtStoX_fp_extend(vReg dst, vReg src) %{
32033201
__ integer_extend_v(as_VectorRegister($dst$$reg), (bt == T_FLOAT ? T_INT : T_LONG),
32043202
Matcher::vector_length(this), as_VectorRegister($src$$reg), T_SHORT);
32053203
__ vsetvli_helper(bt, Matcher::vector_length(this));
3206-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32073204
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg));
32083205
%}
32093206
ins_pipe(pipe_slow);
@@ -3242,7 +3239,6 @@ instruct vcvtItoF(vReg dst, vReg src) %{
32423239
format %{ "vcvtItoF $dst, $src" %}
32433240
ins_encode %{
32443241
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
3245-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32463242
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
32473243
%}
32483244
ins_pipe(pipe_slow);
@@ -3255,7 +3251,6 @@ instruct vcvtItoD(vReg dst, vReg src) %{
32553251
format %{ "vcvtItoD $dst, $src" %}
32563252
ins_encode %{
32573253
__ vsetvli_helper(T_INT, Matcher::vector_length(this), Assembler::mf2);
3258-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32593254
__ vfwcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
32603255
%}
32613256
ins_pipe(pipe_slow);
@@ -3283,7 +3278,6 @@ instruct vcvtLtoF(vReg dst, vReg src) %{
32833278
format %{ "vcvtLtoF $dst, $src" %}
32843279
ins_encode %{
32853280
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2);
3286-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32873281
__ vfncvt_f_x_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
32883282
%}
32893283
ins_pipe(pipe_slow);
@@ -3295,7 +3289,6 @@ instruct vcvtLtoD(vReg dst, vReg src) %{
32953289
format %{ "vcvtLtoD $dst, $src" %}
32963290
ins_encode %{
32973291
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
3298-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32993292
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
33003293
%}
33013294
ins_pipe(pipe_slow);
@@ -3353,7 +3346,6 @@ instruct vcvtFtoD(vReg dst, vReg src) %{
33533346
format %{ "vcvtFtoD $dst, $src" %}
33543347
ins_encode %{
33553348
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2);
3356-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
33573349
__ vfwcvt_f_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
33583350
%}
33593351
ins_pipe(pipe_slow);
@@ -3401,7 +3393,6 @@ instruct vcvtDtoF(vReg dst, vReg src) %{
34013393
format %{ "vcvtDtoF $dst, $src" %}
34023394
ins_encode %{
34033395
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2);
3404-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
34053396
__ vfncvt_f_f_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
34063397
%}
34073398
ins_pipe(pipe_slow);

‎src/hotspot/cpu/riscv/stubGenerator_riscv.cpp

+24-3
Original file line numberDiff line numberDiff line change
@@ -126,8 +126,9 @@ class StubGenerator: public StubCodeGenerator {
126126
// [ return_from_Java ] <--- sp
127127
// [ argument word n ]
128128
// ...
129-
// -34 [ argument word 1 ]
130-
// -33 [ saved f27 ] <--- sp_after_call
129+
// -35 [ argument word 1 ]
130+
// -34 [ saved FRM in Floating-point Control and Status Register ] <--- sp_after_call
131+
// -33 [ saved f27 ]
131132
// -32 [ saved f26 ]
132133
// -31 [ saved f25 ]
133134
// -30 [ saved f24 ]
@@ -164,8 +165,9 @@ class StubGenerator: public StubCodeGenerator {
164165

165166
// Call stub stack layout word offsets from fp
166167
enum call_stub_layout {
167-
sp_after_call_off = -33,
168+
sp_after_call_off = -34,
168169

170+
frm_off = sp_after_call_off,
169171
f27_off = -33,
170172
f26_off = -32,
171173
f25_off = -31,
@@ -213,6 +215,7 @@ class StubGenerator: public StubCodeGenerator {
213215

214216
const Address sp_after_call (fp, sp_after_call_off * wordSize);
215217

218+
const Address frm_save (fp, frm_off * wordSize);
216219
const Address call_wrapper (fp, call_wrapper_off * wordSize);
217220
const Address result (fp, result_off * wordSize);
218221
const Address result_type (fp, result_type_off * wordSize);
@@ -295,6 +298,16 @@ class StubGenerator: public StubCodeGenerator {
295298
__ fsd(f26, f26_save);
296299
__ fsd(f27, f27_save);
297300

301+
__ frrm(t0);
302+
__ sd(t0, frm_save);
303+
// Set frm to the state we need. We do want Round to Nearest. We
304+
// don't want non-IEEE rounding modes.
305+
Label skip_fsrmi;
306+
guarantee(__ RoundingMode::rne == 0, "must be");
307+
__ beqz(t0, skip_fsrmi);
308+
__ fsrmi(__ RoundingMode::rne);
309+
__ bind(skip_fsrmi);
310+
298311
// install Java thread in global register now we have saved
299312
// whatever value it held
300313
__ mv(xthread, c_rarg7);
@@ -414,6 +427,14 @@ class StubGenerator: public StubCodeGenerator {
414427

415428
__ ld(x9, x9_save);
416429

430+
// restore frm
431+
Label skip_fsrm;
432+
__ ld(t0, frm_save);
433+
__ frrm(t1);
434+
__ beq(t0, t1, skip_fsrm);
435+
__ fsrm(t0);
436+
__ bind(skip_fsrm);
437+
417438
__ ld(c_rarg0, call_wrapper);
418439
__ ld(c_rarg1, result);
419440
__ ld(c_rarg2, result_type);

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