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8316859: RISC-V: Disable detection of V through HWCAP
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Backport-of: 311c7461c8c0f5f1524d409736e4cceca8de9000
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luhenry authored and robehn committed Oct 4, 2023
1 parent 9ffec67 commit 69af26c
Showing 1 changed file with 12 additions and 3 deletions.
15 changes: 12 additions & 3 deletions src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -149,12 +149,21 @@ void VM_Version::setup_cpu_available_features() {

void VM_Version::os_aux_features() {
uint64_t auxv = getauxval(AT_HWCAP);
int i = 0;
while (_feature_list[i] != nullptr) {
for (int i = 0; _feature_list[i] != nullptr; i++) {
if (_feature_list[i]->feature_bit() == HWCAP_ISA_V) {
// Special case for V: some dev boards only support RVV version 0.7, while
// the OpenJDK only supports RVV version 1.0. These two versions are not
// compatible with each other. Given the V bit is set through HWCAP on
// some custom kernels, regardless of the version, it can lead to
// generating V instructions on boards that don't support RVV version 1.0
// (ex: Sipeed LicheePi), leading to a SIGILL.
// That is an acceptable workaround as only Linux Kernel v6.5+ supports V,
// and that version already support hwprobe anyway
continue;
}
if ((_feature_list[i]->feature_bit() & auxv) != 0) {
_feature_list[i]->enable_feature();
}
i++;
}
}

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