From d933ae178febb7238743f61a121e80009944b528 Mon Sep 17 00:00:00 2001 From: ArsenyBochkarev Date: Sat, 25 Nov 2023 16:06:38 +0300 Subject: [PATCH] Backport 864b39a89398731bfde9af10c3d7797ff5d05760 --- .../cpu/riscv/macroAssembler_riscv.cpp | 35 ++++++++++--------- .../cpu/riscv/macroAssembler_riscv.hpp | 7 ++-- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp index 29d5d37c387..4afc8ea4b0a 100644 --- a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp @@ -2049,23 +2049,6 @@ void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp1 beq(trial_klass, tmp1, L); } -// Multiply and multiply-accumulate unsigned 64-bit registers. -void MacroAssembler::wide_mul(Register prod_lo, Register prod_hi, Register n, Register m) { - assert_different_registers(prod_lo, prod_hi); - - mul(prod_lo, n, m); - mulhu(prod_hi, n, m); -} -void MacroAssembler::wide_madd(Register sum_lo, Register sum_hi, Register n, - Register m, Register tmp1, Register tmp2) { - assert_different_registers(sum_lo, sum_hi); - assert_different_registers(sum_hi, tmp2); - - wide_mul(tmp1, tmp2, n, m); - cad(sum_lo, sum_lo, tmp1, tmp1); // Add tmp1 to sum_lo with carry output to tmp1 - adc(sum_hi, sum_hi, tmp2, tmp1); // Add tmp2 with carry to sum_hi -} - // Move an oop into a register. void MacroAssembler::movoop(Register dst, jobject obj) { int oop_index; @@ -3557,6 +3540,24 @@ void MacroAssembler::mul_add(Register out, Register in, Register offset, bind(L_end); } +// Multiply and multiply-accumulate unsigned 64-bit registers. +void MacroAssembler::wide_mul(Register prod_lo, Register prod_hi, Register n, Register m) { + assert_different_registers(prod_lo, prod_hi); + + mul(prod_lo, n, m); + mulhu(prod_hi, n, m); +} + +void MacroAssembler::wide_madd(Register sum_lo, Register sum_hi, Register n, + Register m, Register tmp1, Register tmp2) { + assert_different_registers(sum_lo, sum_hi); + assert_different_registers(sum_hi, tmp2); + + wide_mul(tmp1, tmp2, n, m); + cad(sum_lo, sum_lo, tmp1, tmp1); // Add tmp1 to sum_lo with carry output to tmp1 + adc(sum_hi, sum_hi, tmp2, tmp1); // Add tmp2 with carry to sum_hi +} + // add two unsigned input and output carry void MacroAssembler::cad(Register dst, Register src1, Register src2, Register carry) { diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp index 2ac465da4c0..2ae3e9eda35 100644 --- a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp @@ -198,10 +198,6 @@ class MacroAssembler: public Assembler { void store_klass(Register dst, Register src, Register tmp = t0); void cmp_klass(Register oop, Register trial_klass, Register tmp1, Register tmp2, Label &L); - void wide_mul(Register prod_lo, Register prod_hi, Register n, Register m); - void wide_madd(Register sum_lo, Register sum_hi, Register n, - Register m, Register tmp1, Register tmp2); - void encode_klass_not_null(Register r, Register tmp = t0); void decode_klass_not_null(Register r, Register tmp = t0); void encode_klass_not_null(Register dst, Register src, Register tmp); @@ -1188,6 +1184,9 @@ class MacroAssembler: public Assembler { #ifdef COMPILER2 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp); + void wide_mul(Register prod_lo, Register prod_hi, Register n, Register m); + void wide_madd(Register sum_lo, Register sum_hi, Register n, + Register m, Register tmp1, Register tmp2); void cad(Register dst, Register src1, Register src2, Register carry); void cadc(Register dst, Register src1, Register src2, Register carry); void adc(Register dst, Register src1, Register src2, Register carry);