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zifeihanRealFYang
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8330094: RISC-V: Save and restore FRM in the call stub
Reviewed-by: fyang Backport-of: b0496096dc8d7dc7acf28aa006141a3ecea446de
1 parent 5c15483 commit beb06e1

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3 files changed

+25
-13
lines changed

3 files changed

+25
-13
lines changed

src/hotspot/cpu/riscv/frame_riscv.hpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
// Entry frames
132132
// n.b. these values are determined by the layout defined in
133133
// stubGenerator for the Java call stub
134-
entry_frame_after_call_words = 34,
134+
entry_frame_after_call_words = 35,
135135
entry_frame_call_wrapper_offset = -10,
136136

137137
// we don't need a save area

src/hotspot/cpu/riscv/riscv_v.ad

-9
Original file line numberDiff line numberDiff line change
@@ -3000,7 +3000,6 @@ instruct vloadcon(vReg dst, immI0 src) %{
30003000
__ vsetvli_helper(bt, Matcher::vector_length(this));
30013001
__ vid_v(as_VectorRegister($dst$$reg));
30023002
if (is_floating_point_type(bt)) {
3003-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
30043003
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg));
30053004
}
30063005
%}
@@ -3214,7 +3213,6 @@ instruct vcvtBtoX(vReg dst, vReg src) %{
32143213
if (is_floating_point_type(bt)) {
32153214
__ integer_extend_v(as_VectorRegister($dst$$reg), bt == T_FLOAT ? T_INT : T_LONG,
32163215
Matcher::vector_length(this), as_VectorRegister($src$$reg), T_BYTE);
3217-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32183216
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg));
32193217
} else {
32203218
__ integer_extend_v(as_VectorRegister($dst$$reg), bt,
@@ -3261,7 +3259,6 @@ instruct vcvtStoX_fp_extend(vReg dst, vReg src) %{
32613259
__ integer_extend_v(as_VectorRegister($dst$$reg), (bt == T_FLOAT ? T_INT : T_LONG),
32623260
Matcher::vector_length(this), as_VectorRegister($src$$reg), T_SHORT);
32633261
__ vsetvli_helper(bt, Matcher::vector_length(this));
3264-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
32653262
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg));
32663263
%}
32673264
ins_pipe(pipe_slow);
@@ -3300,7 +3297,6 @@ instruct vcvtItoF(vReg dst, vReg src) %{
33003297
format %{ "vcvtItoF $dst, $src" %}
33013298
ins_encode %{
33023299
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
3303-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
33043300
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
33053301
%}
33063302
ins_pipe(pipe_slow);
@@ -3313,7 +3309,6 @@ instruct vcvtItoD(vReg dst, vReg src) %{
33133309
format %{ "vcvtItoD $dst, $src" %}
33143310
ins_encode %{
33153311
__ vsetvli_helper(T_INT, Matcher::vector_length(this), Assembler::mf2);
3316-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
33173312
__ vfwcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
33183313
%}
33193314
ins_pipe(pipe_slow);
@@ -3341,7 +3336,6 @@ instruct vcvtLtoF(vReg dst, vReg src) %{
33413336
format %{ "vcvtLtoF $dst, $src" %}
33423337
ins_encode %{
33433338
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2);
3344-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
33453339
__ vfncvt_f_x_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
33463340
%}
33473341
ins_pipe(pipe_slow);
@@ -3353,7 +3347,6 @@ instruct vcvtLtoD(vReg dst, vReg src) %{
33533347
format %{ "vcvtLtoD $dst, $src" %}
33543348
ins_encode %{
33553349
__ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
3356-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
33573350
__ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
33583351
%}
33593352
ins_pipe(pipe_slow);
@@ -3411,7 +3404,6 @@ instruct vcvtFtoD(vReg dst, vReg src) %{
34113404
format %{ "vcvtFtoD $dst, $src" %}
34123405
ins_encode %{
34133406
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2);
3414-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
34153407
__ vfwcvt_f_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
34163408
%}
34173409
ins_pipe(pipe_slow);
@@ -3459,7 +3451,6 @@ instruct vcvtDtoF(vReg dst, vReg src) %{
34593451
format %{ "vcvtDtoF $dst, $src" %}
34603452
ins_encode %{
34613453
__ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2);
3462-
__ csrwi(CSR_FRM, C2_MacroAssembler::rne);
34633454
__ vfncvt_f_f_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
34643455
%}
34653456
ins_pipe(pipe_slow);

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp

+24-3
Original file line numberDiff line numberDiff line change
@@ -127,8 +127,9 @@ class StubGenerator: public StubCodeGenerator {
127127
// [ return_from_Java ] <--- sp
128128
// [ argument word n ]
129129
// ...
130-
// -34 [ argument word 1 ]
131-
// -33 [ saved f27 ] <--- sp_after_call
130+
// -35 [ argument word 1 ]
131+
// -34 [ saved FRM in Floating-point Control and Status Register ] <--- sp_after_call
132+
// -33 [ saved f27 ]
132133
// -32 [ saved f26 ]
133134
// -31 [ saved f25 ]
134135
// -30 [ saved f24 ]
@@ -165,8 +166,9 @@ class StubGenerator: public StubCodeGenerator {
165166

166167
// Call stub stack layout word offsets from fp
167168
enum call_stub_layout {
168-
sp_after_call_off = -33,
169+
sp_after_call_off = -34,
169170

171+
frm_off = sp_after_call_off,
170172
f27_off = -33,
171173
f26_off = -32,
172174
f25_off = -31,
@@ -214,6 +216,7 @@ class StubGenerator: public StubCodeGenerator {
214216

215217
const Address sp_after_call (fp, sp_after_call_off * wordSize);
216218

219+
const Address frm_save (fp, frm_off * wordSize);
217220
const Address call_wrapper (fp, call_wrapper_off * wordSize);
218221
const Address result (fp, result_off * wordSize);
219222
const Address result_type (fp, result_type_off * wordSize);
@@ -296,6 +299,16 @@ class StubGenerator: public StubCodeGenerator {
296299
__ fsd(f26, f26_save);
297300
__ fsd(f27, f27_save);
298301

302+
__ frrm(t0);
303+
__ sd(t0, frm_save);
304+
// Set frm to the state we need. We do want Round to Nearest. We
305+
// don't want non-IEEE rounding modes.
306+
Label skip_fsrmi;
307+
guarantee(__ RoundingMode::rne == 0, "must be");
308+
__ beqz(t0, skip_fsrmi);
309+
__ fsrmi(__ RoundingMode::rne);
310+
__ bind(skip_fsrmi);
311+
299312
// install Java thread in global register now we have saved
300313
// whatever value it held
301314
__ mv(xthread, c_rarg7);
@@ -415,6 +428,14 @@ class StubGenerator: public StubCodeGenerator {
415428

416429
__ ld(x9, x9_save);
417430

431+
// restore frm
432+
Label skip_fsrm;
433+
__ ld(t0, frm_save);
434+
__ frrm(t1);
435+
__ beq(t0, t1, skip_fsrm);
436+
__ fsrm(t0);
437+
__ bind(skip_fsrm);
438+
418439
__ ld(c_rarg0, call_wrapper);
419440
__ ld(c_rarg1, result);
420441
__ ld(c_rarg2, result_type);

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