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Srinivas Vamsi ParasaPaul Hohensee
Srinivas Vamsi Parasa
authored and
Paul Hohensee
committed
8367694: Fix jtreg test failure when Intel APX is enabled for KNL platforms
Backport-of: e883dec6be8cb2fc44e45a6b4677cca2f4df58ef
1 parent 9305ebf commit e80db07

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+24
-22
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2 files changed

+24
-22
lines changed

‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -13689,15 +13689,15 @@ void Assembler::pdepq(Register dst, Register src1, Address src2) {
1368913689

1369013690
void Assembler::sarxl(Register dst, Register src1, Register src2) {
1369113691
assert(VM_Version::supports_bmi2(), "");
13692-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13692+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1369313693
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes, true);
1369413694
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1369513695
}
1369613696

1369713697
void Assembler::sarxl(Register dst, Address src1, Register src2) {
1369813698
assert(VM_Version::supports_bmi2(), "");
1369913699
InstructionMark im(this);
13700-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13700+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1370113701
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
1370213702
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
1370313703
emit_int8((unsigned char)0xF7);
@@ -13706,15 +13706,15 @@ void Assembler::sarxl(Register dst, Address src1, Register src2) {
1370613706

1370713707
void Assembler::sarxq(Register dst, Register src1, Register src2) {
1370813708
assert(VM_Version::supports_bmi2(), "");
13709-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13709+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1371013710
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes, true);
1371113711
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1371213712
}
1371313713

1371413714
void Assembler::sarxq(Register dst, Address src1, Register src2) {
1371513715
assert(VM_Version::supports_bmi2(), "");
1371613716
InstructionMark im(this);
13717-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13717+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1371813718
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
1371913719
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
1372013720
emit_int8((unsigned char)0xF7);
@@ -13723,15 +13723,15 @@ void Assembler::sarxq(Register dst, Address src1, Register src2) {
1372313723

1372413724
void Assembler::shlxl(Register dst, Register src1, Register src2) {
1372513725
assert(VM_Version::supports_bmi2(), "");
13726-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13726+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1372713727
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes, true);
1372813728
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1372913729
}
1373013730

1373113731
void Assembler::shlxl(Register dst, Address src1, Register src2) {
1373213732
assert(VM_Version::supports_bmi2(), "");
1373313733
InstructionMark im(this);
13734-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13734+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1373513735
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
1373613736
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1373713737
emit_int8((unsigned char)0xF7);
@@ -13740,15 +13740,15 @@ void Assembler::shlxl(Register dst, Address src1, Register src2) {
1374013740

1374113741
void Assembler::shlxq(Register dst, Register src1, Register src2) {
1374213742
assert(VM_Version::supports_bmi2(), "");
13743-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13743+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1374413744
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes, true);
1374513745
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1374613746
}
1374713747

1374813748
void Assembler::shlxq(Register dst, Address src1, Register src2) {
1374913749
assert(VM_Version::supports_bmi2(), "");
1375013750
InstructionMark im(this);
13751-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13751+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1375213752
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
1375313753
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1375413754
emit_int8((unsigned char)0xF7);
@@ -13757,15 +13757,15 @@ void Assembler::shlxq(Register dst, Address src1, Register src2) {
1375713757

1375813758
void Assembler::shrxl(Register dst, Register src1, Register src2) {
1375913759
assert(VM_Version::supports_bmi2(), "");
13760-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13760+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1376113761
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes, true);
1376213762
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1376313763
}
1376413764

1376513765
void Assembler::shrxl(Register dst, Address src1, Register src2) {
1376613766
assert(VM_Version::supports_bmi2(), "");
1376713767
InstructionMark im(this);
13768-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13768+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1376913769
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
1377013770
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
1377113771
emit_int8((unsigned char)0xF7);
@@ -13774,15 +13774,15 @@ void Assembler::shrxl(Register dst, Address src1, Register src2) {
1377413774

1377513775
void Assembler::shrxq(Register dst, Register src1, Register src2) {
1377613776
assert(VM_Version::supports_bmi2(), "");
13777-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13777+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1377813778
int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes, true);
1377913779
emit_int16((unsigned char)0xF7, (0xC0 | encode));
1378013780
}
1378113781

1378213782
void Assembler::shrxq(Register dst, Address src1, Register src2) {
1378313783
assert(VM_Version::supports_bmi2(), "");
1378413784
InstructionMark im(this);
13785-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
13785+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1378613786
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
1378713787
vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
1378813788
emit_int8((unsigned char)0xF7);

‎src/hotspot/cpu/x86/vm_version_x86.cpp‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1015,16 +1015,6 @@ void VM_Version::get_processor_features() {
10151015
_features.clear_feature(CPU_AVX10_2);
10161016
}
10171017

1018-
// Currently APX support is only enabled for targets supporting AVX512VL feature.
1019-
bool apx_supported = os_supports_apx_egprs() && supports_apx_f() && supports_avx512vl();
1020-
if (UseAPX && !apx_supported) {
1021-
warning("UseAPX is not supported on this CPU, setting it to false");
1022-
FLAG_SET_DEFAULT(UseAPX, false);
1023-
}
1024-
1025-
if (!UseAPX) {
1026-
_features.clear_feature(CPU_APX_F);
1027-
}
10281018

10291019
if (UseAVX < 2) {
10301020
_features.clear_feature(CPU_AVX2);
@@ -1048,6 +1038,7 @@ void VM_Version::get_processor_features() {
10481038
_features.clear_feature(CPU_VZEROUPPER);
10491039
_features.clear_feature(CPU_AVX512BW);
10501040
_features.clear_feature(CPU_AVX512VL);
1041+
_features.clear_feature(CPU_APX_F);
10511042
_features.clear_feature(CPU_AVX512DQ);
10521043
_features.clear_feature(CPU_AVX512_VNNI);
10531044
_features.clear_feature(CPU_AVX512_VAES);
@@ -1067,6 +1058,17 @@ void VM_Version::get_processor_features() {
10671058
}
10681059
}
10691060

1061+
// Currently APX support is only enabled for targets supporting AVX512VL feature.
1062+
bool apx_supported = os_supports_apx_egprs() && supports_apx_f() && supports_avx512vl();
1063+
if (UseAPX && !apx_supported) {
1064+
warning("UseAPX is not supported on this CPU, setting it to false");
1065+
FLAG_SET_DEFAULT(UseAPX, false);
1066+
}
1067+
1068+
if (!UseAPX) {
1069+
_features.clear_feature(CPU_APX_F);
1070+
}
1071+
10701072
if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
10711073
_has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
10721074
FLAG_SET_ERGO(IntelJccErratumMitigation, _has_intel_jcc_erratum);

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