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8285802: AArch64: Consistently handle offsets in MacroAssembler as 64-bit quantities #50

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8285802: AArch64: Consistently handle offsets in MacroAssembler as 64-bit quantities #50

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10 changes: 5 additions & 5 deletions hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2016,11 +2016,11 @@ void MacroAssembler::warn(const char* msg) {

// If a constant does not fit in an immediate field, generate some
// number of MOV instructions and then perform the operation.
void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2) {
assert(Rd != zr, "Rd = zr and not setting flags?");
if (operand_valid_for_add_sub_immediate((int)imm)) {
if (operand_valid_for_add_sub_immediate(imm)) {
(this->*insn1)(Rd, Rn, imm);
} else {
if (uabs(imm) < (1 << 24)) {
Expand All @@ -2036,15 +2036,15 @@ void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned im

// Seperate vsn which sets the flags. Optimisations are more restricted
// because we must set the flags correctly.
void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2) {
if (operand_valid_for_add_sub_immediate((int)imm)) {
if (operand_valid_for_add_sub_immediate(imm)) {
(this->*insn1)(Rd, Rn, imm);
} else {
assert_different_registers(Rd, Rn);
assert(Rd != zr, "overflow in immediate operand");
mov(Rd, (uint64_t)imm);
mov(Rd, imm);
(this->*insn2)(Rd, Rn, Rd, LSL, 0);
}
}
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14 changes: 7 additions & 7 deletions hotspot/src/cpu/aarch64/vm/macroAssembler_aarch64.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ class MacroAssembler: public Assembler {

template<class T>
inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
inline void cmp(Register Rd, unsigned imm) { Assembler::subs(zr, Rd, imm); }

inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
Expand All @@ -202,7 +202,7 @@ class MacroAssembler: public Assembler {

inline void movw(Register Rd, Register Rn) {
if (Rd == sp || Rn == sp) {
addw(Rd, Rn, 0U);
Assembler::addw(Rd, Rn, 0U);
} else {
orrw(Rd, zr, Rn);
}
Expand All @@ -211,7 +211,7 @@ class MacroAssembler: public Assembler {
assert(Rd != r31_sp && Rn != r31_sp, "should be");
if (Rd == Rn) {
} else if (Rd == sp || Rn == sp) {
add(Rd, Rn, 0U);
Assembler::add(Rd, Rn, 0U);
} else {
orr(Rd, zr, Rn);
}
Expand Down Expand Up @@ -1074,16 +1074,16 @@ class MacroAssembler: public Assembler {

// If a constant does not fit in an immediate field, generate some
// number of MOV instructions and then perform the operation
void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2);
// Seperate vsn which sets the flags
void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
add_sub_imm_insn insn1,
add_sub_reg_insn insn2);

#define WRAP(INSN) \
void INSN(Register Rd, Register Rn, unsigned imm) { \
void INSN(Register Rd, Register Rn, uint64_t imm) { \
wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
} \
\
Expand All @@ -1105,7 +1105,7 @@ class MacroAssembler: public Assembler {

#undef WRAP
#define WRAP(INSN) \
void INSN(Register Rd, Register Rn, unsigned imm) { \
void INSN(Register Rd, Register Rn, uint64_t imm) { \
wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
} \
\
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2 changes: 1 addition & 1 deletion hotspot/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
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Expand Up @@ -3449,7 +3449,7 @@ class StubGenerator: public StubCodeGenerator {
assert(is_even(framesize/2), "sp not 16-byte aligned");

// lr and fp are already in place
__ sub(sp, rfp, ((unsigned)framesize-4) << LogBytesPerInt); // prolog
__ sub(sp, rfp, ((uint64_t)framesize-4) << LogBytesPerInt); // prolog

int frame_complete = __ pc() - start;

Expand Down