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8242029: AArch64: skip G1 array copy pre-barrier if marking not active

Reviewed-by: aph
  • Loading branch information
nick-arm committed Apr 8, 2020
1 parent d8539a5 commit 67fd181eb8e0013d4f6ad2f0862ab1f15c0d0189
Showing with 15 additions and 1 deletion.
  1. +15 −1 src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -47,6 +47,18 @@ void G1BarrierSetAssembler::gen_write_ref_array_pre_barrier(MacroAssembler* masm
Register addr, Register count, RegSet saved_regs) {
bool dest_uninitialized = (decorators & IS_DEST_UNINITIALIZED) != 0;
if (!dest_uninitialized) {
Label done;
Address in_progress(rthread, in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset()));

// Is marking active?
if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
__ ldrw(rscratch1, in_progress);
} else {
assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
__ ldrb(rscratch1, in_progress);
}
__ cbzw(rscratch1, done);

__ push(saved_regs, sp);
if (count == c_rarg0) {
if (addr == c_rarg1) {
@@ -68,6 +80,8 @@ void G1BarrierSetAssembler::gen_write_ref_array_pre_barrier(MacroAssembler* masm
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_array_pre_oop_entry), 2);
}
__ pop(saved_regs, sp);

__ bind(done);
}
}

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