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8261142: AArch64: Incorrect instruction encoding when right-shifting …
…vectors with shift amount equals to the element width

Reviewed-by: njian, aph
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Dong Bo authored and Fei Yang committed Mar 3, 2021
1 parent 044e2a2 commit c15801e98ccd2d94cc1faa67288b7730ca230f29
@@ -2685,6 +2685,7 @@ void mvnw(Register Rd, Register Rm,
* 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
* (1D is RESERVED) \
*/ \
assert(!isSHR || (isSHR && (shift != 0)), "Zero right shift"); \
assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
int encodedShift = isSHR ? cVal - shift : cVal + shift; \
@@ -527,6 +527,33 @@ class MacroAssembler: public Assembler {
orr(Vd, T, Vn, Vn);
}

// AdvSIMD shift by immediate.
// These are "user friendly" variants which allow a shift count of 0.
#define WRAP(INSN) \
void INSN(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift) { \
if (shift == 0) { \
SIMD_Arrangement arrange = (T & 1) == 0 ? T8B : T16B; \
Assembler::orr(Vd, arrange, Vn, Vn); \
} else { \
Assembler::INSN(Vd, T, Vn, shift); \
} \
} \

WRAP(shl) WRAP(sshr) WRAP(ushr)
#undef WRAP

#define WRAP(INSN) \
void INSN(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift) { \
if (shift == 0) { \
Assembler::addv(Vd, T, Vd, Vn); \
} else { \
Assembler::INSN(Vd, T, Vn, shift); \
} \
} \

WRAP(usra) WRAP(ssra)
#undef WRAP

public:

// Generalized Test Bit And Branch, including a "far" variety which

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