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Merge master #542

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4ba7613
8267332: xor value should handle bounded values
May 21, 2021
ec8a809
8267119: switch expressions lack support for deferred type-checking
May 21, 2021
94cfeb9
8256155: Allow multiple large page sizes to be used on Linux
May 21, 2021
8f10c5a
8267190: Optimize Vector API test operations
May 21, 2021
fe33343
8256304: should MonitorUsedDeflationThreshold be experimental or diag…
May 21, 2021
72c9567
8263486: Clean up MTLSurfaceDataBase.h
aghaisas May 22, 2021
2462316
8261354: SIGSEGV at MethodIteratorHost
May 22, 2021
4023646
8266528: Optimize C2 VerifyIterativeGVN execution time
May 22, 2021
71e2fa2
8267531: [x86] Assembler::andb(Address,Register) encoding is incorrect
shipilev May 22, 2021
6288a99
8267404: vmTestbase/vm/mlvm/anonloader/stress/oome/metaspace/Test.jav…
DamonFool May 22, 2021
4d26f22
8264304: Create implementation for NSAccessibilityToolbar protocol peer
May 23, 2021
3113910
8267553: Extra JavaThread assignment in ClassLoader::create_class_pat…
May 24, 2021
54520fb
8267580: The method JavacParser#peekToken is wrong when the first par…
lgxbslgx May 24, 2021
49f622c
8208747: [a11y] [macos] In Optionpane Demo, inside ComponentDialog Ex…
May 24, 2021
f453166
8267578: Remove unnecessary preview checks
lgxbslgx May 24, 2021
d8e6e28
8267544: (test) rmi test NonLocalSkeleton fails if network has multip…
May 24, 2021
f5562f1
8258535: jvm.ClassReader should set the accessor to the corresponding…
May 24, 2021
f2d880c
8266400: importkeystore fails to a password less pkcs12 keystore
May 24, 2021
838a007
8267584: The java.security.krb5.realm system property only needs to b…
wangweij May 24, 2021
f04db5f
8224158: assertion related to NPE at DynamicCallSiteDesc::withArgs sh…
May 24, 2021
640a2af
8267184: Add -Djava.security.manager=allow to tests calling System.se…
wangweij May 24, 2021
bb085f6
8265362: java/net/Socket/UdpSocket.java fails with "java.net.BindExce…
May 24, 2021
a5467ae
8267423: Fix copyrights in jpackage tests
May 24, 2021
209769b
8267347: CDS record_linking_constraint asserts with unregistered class
iklam May 24, 2021
ebc9357
8267329: Modernize Javadoc code to use instanceof with pattern matching
May 24, 2021
f690959
8267446: Taskqueue code fails with assert(bottom_relaxed() == age_top…
May 24, 2021
c519ba2
8267614: Outline VarHandleGuards exact behavior checks
cl4es May 24, 2021
de27da7
8267431: Rename InstanceKlass::has_old_class_version to can_be_verifi…
calvinccheung May 25, 2021
461a3fe
8261478: InstanceKlass::set_classpath_index does not match comments
calvinccheung May 25, 2021
b4d4884
8267126: javadoc should show "line and caret" for diagnostics.
jonathan-gibbons May 25, 2021
123cdd1
8264973: AArch64: Optimize vector max/min/add reduction of two intege…
May 25, 2021
2e8812d
8265129: Add intrinsic support for JVM.getClassId
May 25, 2021
31d0f0d
8248843: java in source-file mode suggests javac-only options
May 25, 2021
d86f916
8267066: New NSAccessibility peers should return they roles and subro…
May 25, 2021
0a03fc8
8255674: SSLEngine class description is missing "case" in switch stat…
May 25, 2021
a52c4ed
8267110: Update java.util to use instanceof pattern variable
pconcannon May 25, 2021
66b190e
8267612: Declare package-private VarHandle.AccessMode/AccessType counts
cl4es May 25, 2021
b403d39
8267213: cpuinfo_segv is incorrectly triaged as execution protection …
DamonFool May 25, 2021
86a8f44
8267317: Remove DeferredTypeCompleter
mcimadamore May 25, 2021
5a5b807
8267633: Clarify documentation of (Doc)TreeScanner
pavelrappo May 25, 2021
cc687fd
8267575: Add new documentation group in HtmlStyle
jonathan-gibbons May 25, 2021
2ef2450
8263445: Duplicate key compiler.err.expected.module in compiler.prope…
May 25, 2021
594d454
8267574: Dead code in HtmlStyle/HtmlDocletWriter
jonathan-gibbons May 25, 2021
0b77359
8224243: Add implSpec's to AccessibleObject and seal Executable
jddarcy May 25, 2021
e751b7b
8267683: rfc7301Grease8F value not displayed correctly in SSLParamete…
May 25, 2021
c20ca42
8267691: Change table to obsolete CriticalJNINatives in JDK 18, not 17
coleenp May 25, 2021
5aa45f2
8267403: tools/jpackage/share/FileAssociationsTest.java#id0 failed wi…
May 25, 2021
a98e476
8267311: vmTestbase/gc/gctests/StringInternGC/StringInternGC.java eve…
DamonFool May 25, 2021
d0d2ddc
8267651: runtime/handshake/HandshakeTimeoutTest.java times out when d…
May 25, 2021
ac36b7d
8267452: Delegate forEachRemaining in Spliterators.iterator()
May 26, 2021
b33b8bc
8267750: Incomplete fix for JDK-8267683
May 26, 2021
0394416
8267468: Rename refill waster counters in ThreadLocalAllocBuffer
albertnetymk May 26, 2021
9d305b9
8252372: Check if cloning is required to move loads out of loops in P…
rwestrel May 26, 2021
083416d
8267130: Memory Overflow in Disassembler::load_library
May 26, 2021
bf8d4a8
8267583: jmod fails on symlink to class file
sundararajana May 26, 2021
f632254
8267221: jshell feedback is incorrect when creating method with array…
May 26, 2021
4343997
8267708: Remove references to com.sun.tools.javadoc.**
pavelrappo May 26, 2021
45e0597
8264302: Create implementation for Accessibility native peer for Spli…
May 26, 2021
9c346a1
8266963: Remove safepoint poll introduced in 8262443 due to reentranc…
linade May 26, 2021
a4c46e1
8263202: Update Hebrew/Indonesian/Yiddish ISO 639 language codes to c…
naotoj May 26, 2021
de91643
8267611: Print more info when pointer_delta assert fails
stefank May 26, 2021
c59484e
8267653: Remove Mutex::_safepoint_check_sometimes
coleenp May 26, 2021
8c4719a
8265248: Implementation Specific Properties: change prefix, plus add …
JoeWang-Java May 26, 2021
e630235
8266851: Implement JEP 403: Strongly Encapsulate JDK Internals
mbreinhold May 26, 2021
a859d87
8267721: Enable sun/security/pkcs11 tests for Amazon Linux 2 AArch64
eastig May 26, 2021
0fc7c8d
8267751: (test) jtreg.SkippedException has no serial VersionUID
May 26, 2021
1899f02
8267805: Add UseVtableBasedCHA to the list of JVM flags known to jtreg
May 26, 2021
6ffa3e6
8267754: cds/appcds/loaderConstraints/LoaderConstraintsTest.java fail…
DamonFool May 26, 2021
37bc4e2
8263635: Add --servername option to jhsdb debugd
YaSuenag May 27, 2021
bfa46f0
8252476: as_Worker_thread() doesn't check what it intends
albertnetymk May 27, 2021
7278f56
8267800: Remove the '_dirty' set in BCEscapeAnalyzer
May 27, 2021
85f6165
8267817: [TEST] Remove unnecessary init in test/micro/org/openjdk/ben…
May 27, 2021
3623abb
8263087: Add a MethodHandle combinator that switches over a set of Me…
JornVernee May 27, 2021
ec65cf8
8240347: remove undocumented options from jlink --help message
sundararajana May 27, 2021
bea4109
8187649: ArrayIndexOutOfBoundsException in java.util.JapaneseImperial…
naotoj May 27, 2021
10a6f5d
8230623: Extract command-line help for -Xlint sub-options to new --he…
lgxbslgx May 27, 2021
ef368b3
8265836: OperatingSystemImpl.getCpuLoad() returns incorrect CPU load …
tanghaoth90 May 27, 2021
23189a1
8191786: Thread-SMR hash table size should be dynamic
May 27, 2021
0754266
8267709: Investigate differences between HtmlStyle and stylesheet.css
jonathan-gibbons May 27, 2021
7c85f35
8267123: Remove RMI Activation
May 27, 2021
41185d3
8229517: Support for optional asynchronous/buffered logging
May 27, 2021
ae258f1
8265418: Clean-up redundant null-checks of Class.getPackageName()
stsypanov May 27, 2021
8a31c07
8267886: ProblemList javax/management/remote/mandatory/connection/RMI…
May 27, 2021
7f52c50
8182043: Access to Windows Large Icons
May 27, 2021
95b1fa7
8267529: StringJoiner can create a String that breaks String::equals
cl4es May 27, 2021
0c9daa7
8265029: Preserve SIZED characteristics on slice operations (skip, li…
May 28, 2021
6eb9114
8266877: Missing local debug information when debugging JEP-330
JaroslavTulach May 28, 2021
97ec5ad
8265753: Remove manual JavaThread transitions to blocked
robehn May 28, 2021
1d2c7ac
8267555: Fix class file version during redefinition after 8238048
May 28, 2021
d85793d
Automatic merge of jdk:master into master
May 28, 2021
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -156,13 +156,6 @@ String getID() {
return id;
}

String getJavaID() {
// Tweak ISO compatibility for bundle generation
return id.replaceFirst("^he", "iw")
.replaceFirst("^id", "in")
.replaceFirst("^yi", "ji");
}

boolean isRoot() {
return "root".equals(id);
}
@@ -536,7 +536,6 @@ private static void convertBundles(List<Bundle> bundles) throws Exception {
Map<String, Object> targetMap = bundle.getTargetMap();
EnumSet<Bundle.Type> bundleTypes = bundle.getBundleTypes();
var id = bundle.getID();
var javaId = bundle.getJavaID();

if (bundle.isRoot()) {
// Add DateTimePatternChars because CLDR no longer supports localized patterns.
@@ -548,31 +547,31 @@ private static void convertBundles(List<Bundle> bundles) throws Exception {
if (bundleTypes.contains(Bundle.Type.LOCALENAMES)) {
Map<String, Object> localeNamesMap = extractLocaleNames(targetMap, id);
if (!localeNamesMap.isEmpty() || bundle.isRoot()) {
bundleGenerator.generateBundle("util", "LocaleNames", javaId, true, localeNamesMap, BundleType.OPEN);
bundleGenerator.generateBundle("util", "LocaleNames", id, true, localeNamesMap, BundleType.OPEN);
}
}
if (bundleTypes.contains(Bundle.Type.CURRENCYNAMES)) {
Map<String, Object> currencyNamesMap = extractCurrencyNames(targetMap, id, bundle.getCurrencies());
if (!currencyNamesMap.isEmpty() || bundle.isRoot()) {
bundleGenerator.generateBundle("util", "CurrencyNames", javaId, true, currencyNamesMap, BundleType.OPEN);
bundleGenerator.generateBundle("util", "CurrencyNames", id, true, currencyNamesMap, BundleType.OPEN);
}
}
if (bundleTypes.contains(Bundle.Type.TIMEZONENAMES)) {
Map<String, Object> zoneNamesMap = extractZoneNames(targetMap, id);
if (!zoneNamesMap.isEmpty() || bundle.isRoot()) {
bundleGenerator.generateBundle("util", "TimeZoneNames", javaId, true, zoneNamesMap, BundleType.TIMEZONE);
bundleGenerator.generateBundle("util", "TimeZoneNames", id, true, zoneNamesMap, BundleType.TIMEZONE);
}
}
if (bundleTypes.contains(Bundle.Type.CALENDARDATA)) {
Map<String, Object> calendarDataMap = extractCalendarData(targetMap, id);
if (!calendarDataMap.isEmpty() || bundle.isRoot()) {
bundleGenerator.generateBundle("util", "CalendarData", javaId, true, calendarDataMap, BundleType.PLAIN);
bundleGenerator.generateBundle("util", "CalendarData", id, true, calendarDataMap, BundleType.PLAIN);
}
}
if (bundleTypes.contains(Bundle.Type.FORMATDATA)) {
Map<String, Object> formatDataMap = extractFormatData(targetMap, id);
if (!formatDataMap.isEmpty() || bundle.isRoot()) {
bundleGenerator.generateBundle("text", "FormatData", javaId, true, formatDataMap, BundleType.PLAIN);
bundleGenerator.generateBundle("text", "FormatData", id, true, formatDataMap, BundleType.PLAIN);
}
}

@@ -1,5 +1,5 @@
#
# Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2011, 2021, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
@@ -25,10 +25,6 @@

include LauncherCommon.gmk

$(eval $(call SetupBuildLauncher, rmid, \
MAIN_CLASS := sun.rmi.server.Activation, \
))

$(eval $(call SetupBuildLauncher, rmiregistry, \
MAIN_CLASS := sun.rmi.registry.RegistryImpl, \
))
@@ -8735,6 +8735,61 @@ instruct castLL(iRegL dst)
ins_pipe(pipe_class_empty);
%}

instruct castFF(vRegF dst)
%{
match(Set dst (CastFF dst));

size(0);
format %{ "# castFF of $dst" %}
ins_encode(/* empty encoding */);
ins_cost(0);
ins_pipe(pipe_class_empty);
%}

instruct castDD(vRegD dst)
%{
match(Set dst (CastDD dst));

size(0);
format %{ "# castDD of $dst" %}
ins_encode(/* empty encoding */);
ins_cost(0);
ins_pipe(pipe_class_empty);
%}

instruct castVVD(vecD dst)
%{
match(Set dst (CastVV dst));

size(0);
format %{ "# castVV of $dst" %}
ins_encode(/* empty encoding */);
ins_cost(0);
ins_pipe(pipe_class_empty);
%}

instruct castVVX(vecX dst)
%{
match(Set dst (CastVV dst));

size(0);
format %{ "# castVV of $dst" %}
ins_encode(/* empty encoding */);
ins_cost(0);
ins_pipe(pipe_class_empty);
%}

instruct castVV(vReg dst)
%{
match(Set dst (CastVV dst));

size(0);
format %{ "# castVV of $dst" %}
ins_encode(/* empty encoding */);
ins_cost(0);
ins_pipe(pipe_class_empty);
%}

// ============================================================================
// Atomic operation instructions
//
@@ -874,43 +874,39 @@ instruct reduce_min4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlag
ins_pipe(pipe_slow);
%}

instruct reduce_max2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
instruct reduce_max2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "dup $tmp, T2D, $vsrc\n\t"
"smaxv $tmp, T4S, $tmp\n\t"
format %{ "smaxp $tmp, T2S, $vsrc, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction2I"
%}
ins_encode %{
__ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
__ smaxv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
__ smaxp(as_FloatRegister($tmp$$reg), __ T2S, as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}

instruct reduce_min2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
instruct reduce_min2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "dup $tmp, T2D, $vsrc\n\t"
"sminv $tmp, T4S, $tmp\n\t"
format %{ "sminp $tmp, T2S, $vsrc, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction2I"
%}
ins_encode %{
__ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
__ sminv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
__ sminp(as_FloatRegister($tmp$$reg), __ T2S, as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
@@ -4053,22 +4049,21 @@ instruct replicate2D(vecX dst, vRegD src)

// ====================REDUCTION ARITHMETIC====================================

instruct reduce_add2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp, iRegINoSp tmp2)
instruct reduce_add2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP tmp, TEMP tmp2);
format %{ "umov $tmp, $vsrc, S, 0\n\t"
"umov $tmp2, $vsrc, S, 1\n\t"
"addw $tmp, $isrc, $tmp\n\t"
"addw $dst, $tmp, $tmp2\t# add reduction2I"
effect(TEMP vtmp, TEMP itmp);
format %{ "addpv $vtmp, T2S, $vsrc, $vsrc\n\t"
"umov $itmp, $vtmp, S, 0\n\t"
"addw $dst, $itmp, $isrc\t# add reduction2I"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
__ umov($tmp2$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
__ addw($tmp$$Register, $isrc$$Register, $tmp$$Register);
__ addw($dst$$Register, $tmp$$Register, $tmp2$$Register);
__ addpv(as_FloatRegister($vtmp$$reg), __ T2S,
as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
__ addw($dst$$Register, $itmp$$Register, $isrc$$Register);
%}
ins_pipe(pipe_class_default);
%}
@@ -496,21 +496,19 @@ REDUCE_MAX_MIN_INT(min, 8, S, X, Min, s, LT)
REDUCE_MAX_MIN_INT(min, 4, I, X, Min, u, LT)
dnl
define(`REDUCE_MAX_MIN_2I', `
instruct reduce_$1`'2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
instruct reduce_$1`'2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "dup $tmp, T2D, $vsrc\n\t"
"s$1v $tmp, T4S, $tmp\n\t"
format %{ "s$1p $tmp, T2S, $vsrc, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc $3\t# $1 reduction2I"
%}
ins_encode %{
__ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
__ s$1v(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
__ s$1p(as_FloatRegister($tmp$$reg), __ T2S, as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::$3);
@@ -1603,27 +1601,22 @@ dnl
// ====================REDUCTION ARITHMETIC====================================
dnl
define(`REDUCE_ADD_INT', `
instruct reduce_add$1$2`'(iRegINoSp dst, iRegIorL2I isrc, vec$3 vsrc, ifelse($1, 2, iRegINoSp tmp, vecX vtmp), iRegINoSp ifelse($1, 2, tmp2, itmp))
instruct reduce_add$1$2`'(iRegINoSp dst, iRegIorL2I isrc, vec$3 vsrc, vec$3 vtmp, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP ifelse($1, 2, tmp, vtmp), TEMP ifelse($1, 2, tmp2, itmp));
format %{ ifelse($1, 2, `"umov $tmp, $vsrc, S, 0\n\t"
"umov $tmp2, $vsrc, S, 1\n\t"
"addw $tmp, $isrc, $tmp\n\t"
"addw $dst, $tmp, $tmp2\t# add reduction2I"',`"addv $vtmp, T4S, $vsrc\n\t"
effect(TEMP vtmp, TEMP itmp);
format %{ ifelse($1, 2, `"addpv $vtmp, T2S, $vsrc, $vsrc\n\t"',`"addv $vtmp, T4S, $vsrc\n\t"')
"umov $itmp, $vtmp, S, 0\n\t"
"addw $dst, $itmp, $isrc\t# add reduction4I"')
"addw $dst, $itmp, $isrc\t# add reduction$1I"
%}
ins_encode %{
ifelse($1, 2, `__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
__ umov($tmp2$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
__ addw($tmp$$Register, $isrc$$Register, $tmp$$Register);
__ addw($dst$$Register, $tmp$$Register, $tmp2$$Register);', `__ addv(as_FloatRegister($vtmp$$reg), __ T4S,
as_FloatRegister($vsrc$$reg));
ifelse($1, 2, `__ addpv(as_FloatRegister($vtmp$$reg), __ T2S,
as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));', `__ addv(as_FloatRegister($vtmp$$reg), __ T4S,
as_FloatRegister($vsrc$$reg));')
__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
__ addw($dst$$Register, $itmp$$Register, $isrc$$Register);')
__ addw($dst$$Register, $itmp$$Register, $isrc$$Register);
%}
ins_pipe(pipe_class_default);
%}')dnl
@@ -2404,6 +2404,8 @@ void mvnw(Register Rd, Register Rm,
INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(maxv, 0, 0b011001, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(minv, 0, 0b011011, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(smaxp, 0, 0b101001, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(sminp, 0, 0b101011, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
INSN(cmeq, 1, 0b100011, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(cmgt, 0, 0b001101, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
INSN(cmge, 0, 0b001111, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
@@ -5182,6 +5182,39 @@ instruct castLL( iRegL dst ) %{
ins_pipe(empty);
%}

instruct castFF( regF dst ) %{
match(Set dst (CastFF dst));
format %{ "! castFF of $dst" %}
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe(empty);
%}

instruct castDD( regD dst ) %{
match(Set dst (CastDD dst));
format %{ "! castDD of $dst" %}
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe(empty);
%}

instruct castVVD( vecD dst ) %{
match(Set dst (CastVV dst));
format %{ "! castVV of $dst" %}
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe(empty);
%}

instruct castVVX( vecX dst ) %{
match(Set dst (CastVV dst));
format %{ "! castVV of $dst" %}
ins_encode( /*empty encoding*/ );
ins_cost(0);
ins_pipe(empty);
%}


//----------Arithmetic Instructions--------------------------------------------
// Addition Instructions
// Register Addition
@@ -10335,6 +10335,38 @@ instruct castLL(iRegLdst dst) %{
ins_pipe(pipe_class_default);
%}

instruct castFF(regF dst) %{
match(Set dst (CastFF dst));
format %{ " -- \t// castFF of $dst" %}
size(0);
ins_encode( /*empty*/ );
ins_pipe(pipe_class_default);
%}

instruct castDD(regD dst) %{
match(Set dst (CastDD dst));
format %{ " -- \t// castDD of $dst" %}
size(0);
ins_encode( /*empty*/ );
ins_pipe(pipe_class_default);
%}

instruct castVV8(iRegLdst dst) %{
match(Set dst (CastVV dst));
format %{ " -- \t// castVV of $dst" %}
size(0);
ins_encode( /*empty*/ );
ins_pipe(pipe_class_default);
%}

instruct castVV16(vecX dst) %{
match(Set dst (CastVV dst));
format %{ " -- \t// castVV of $dst" %}
size(0);
ins_encode( /*empty*/ );
ins_pipe(pipe_class_default);
%}

instruct checkCastPP(iRegPdst dst) %{
match(Set dst (CheckCastPP dst));
format %{ " -- \t// checkcastPP of $dst" %}