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Xiaohong Gong
committed
8283145: [vector] Add the compiler IR and aarch64 support for count leading and trailing zeros
Reviewed-by: njian, jbhateja
1 parent 701e6ba commit 03e4da7

14 files changed

+434
-122
lines changed

‎src/hotspot/cpu/aarch64/aarch64_neon.ad

+78-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2-
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
1+
// Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
2+
// Copyright (c) 2020, 2022, Arm Limited. All rights reserved.
33
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
//
55
// This code is free software; you can redistribute it and/or modify it
@@ -5649,3 +5649,79 @@ instruct vmask_tolong16B(iRegLNoSp dst, vecX src) %{
56495649
%}
56505650
ins_pipe(pipe_slow);
56515651
%}
5652+
5653+
//------------------------- CountLeadingZerosV -----------------------------
5654+
5655+
instruct countLeadingZerosVD(vecD dst, vecD src) %{
5656+
predicate(n->as_Vector()->length_in_bytes() == 8);
5657+
match(Set dst (CountLeadingZerosV src));
5658+
ins_cost(INSN_COST);
5659+
format %{ "countLeadingZerosV $dst, $src\t# vector (8B/4H/2S)" %}
5660+
ins_encode %{
5661+
BasicType bt = Matcher::vector_element_basic_type(this);
5662+
Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), false);
5663+
__ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($src$$reg));
5664+
%}
5665+
ins_pipe(pipe_slow);
5666+
%}
5667+
5668+
instruct countLeadingZerosVX(vecX dst, vecX src) %{
5669+
predicate(n->as_Vector()->length_in_bytes() == 16);
5670+
match(Set dst (CountLeadingZerosV src));
5671+
ins_cost(INSN_COST);
5672+
format %{ "countLeadingZerosV $dst, $src\t# vector (16B/8H/4S/2D)" %}
5673+
ins_encode %{
5674+
BasicType bt = Matcher::vector_element_basic_type(this);
5675+
Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), true);
5676+
if (bt != T_LONG) {
5677+
__ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($src$$reg));
5678+
} else {
5679+
__ umov(rscratch1, as_FloatRegister($src$$reg), __ D, 0);
5680+
__ clz(rscratch1, rscratch1);
5681+
__ mov(as_FloatRegister($dst$$reg), __ D, 0, rscratch1);
5682+
__ umov(rscratch1, as_FloatRegister($src$$reg), __ D, 1);
5683+
__ clz(rscratch1, rscratch1);
5684+
__ mov(as_FloatRegister($dst$$reg), __ D, 1, rscratch1);
5685+
}
5686+
%}
5687+
ins_pipe(pipe_slow);
5688+
%}
5689+
5690+
//------------------------- CountTrailingZerosV ----------------------------
5691+
5692+
instruct countTrailingZerosVD(vecD dst, vecD src) %{
5693+
predicate(n->as_Vector()->length_in_bytes() == 8);
5694+
match(Set dst (CountTrailingZerosV src));
5695+
ins_cost(3 * INSN_COST);
5696+
format %{ "countTrailingZerosV $dst, $src\t# vector (8B/4H/2S)" %}
5697+
ins_encode %{
5698+
BasicType bt = Matcher::vector_element_basic_type(this);
5699+
Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), false);
5700+
__ neon_reverse_bits(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, false);
5701+
__ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($dst$$reg));
5702+
%}
5703+
ins_pipe(pipe_slow);
5704+
%}
5705+
5706+
instruct countTrailingZerosVX(vecX dst, vecX src) %{
5707+
predicate(n->as_Vector()->length_in_bytes() == 16);
5708+
match(Set dst (CountTrailingZerosV src));
5709+
ins_cost(3 * INSN_COST);
5710+
format %{ "countTrailingZerosV $dst, $src\t# vector (16B/8H/4S/2D)" %}
5711+
ins_encode %{
5712+
BasicType bt = Matcher::vector_element_basic_type(this);
5713+
Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), true);
5714+
__ neon_reverse_bits(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, true);
5715+
if (bt != T_LONG) {
5716+
__ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($dst$$reg));
5717+
} else {
5718+
__ umov(rscratch1, as_FloatRegister($dst$$reg), __ D, 0);
5719+
__ clz(rscratch1, rscratch1);
5720+
__ mov(as_FloatRegister($dst$$reg), __ D, 0, rscratch1);
5721+
__ umov(rscratch1, as_FloatRegister($dst$$reg), __ D, 1);
5722+
__ clz(rscratch1, rscratch1);
5723+
__ mov(as_FloatRegister($dst$$reg), __ D, 1, rscratch1);
5724+
}
5725+
%}
5726+
ins_pipe(pipe_slow);
5727+
%}

‎src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

+56-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2-
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
1+
// Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
2+
// Copyright (c) 2020, 2022, Arm Limited. All rights reserved.
33
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
//
55
// This code is free software; you can redistribute it and/or modify it
@@ -2513,3 +2513,57 @@ instruct vmask_tolong16B(iRegLNoSp dst, vecX src) %{
25132513
%}
25142514
ins_pipe(pipe_slow);
25152515
%}
2516+
2517+
dnl
2518+
dnl CLTZ_D($1 )
2519+
dnl CLTZ_D(op_name)
2520+
define(`CLTZ_D', `
2521+
instruct count$1D(vecD dst, vecD src) %{
2522+
predicate(n->as_Vector()->length_in_bytes() == 8);
2523+
match(Set dst (Count$1 src));
2524+
ins_cost(ifelse($1, `TrailingZerosV', `3 * ', `')INSN_COST);
2525+
format %{ "count$1 $dst, $src\t# vector (8B/4H/2S)" %}
2526+
ins_encode %{
2527+
BasicType bt = Matcher::vector_element_basic_type(this);
2528+
Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), false);dnl
2529+
ifelse($1, `TrailingZerosV', `
2530+
__ neon_reverse_bits(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, false);', `')
2531+
__ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg));
2532+
%}
2533+
ins_pipe(pipe_slow);
2534+
%}')dnl
2535+
dnl
2536+
dnl CLTZ_X($1 )
2537+
dnl CLTZ_X(op_name)
2538+
define(`CLTZ_X', `
2539+
instruct count$1X(vecX dst, vecX src) %{
2540+
predicate(n->as_Vector()->length_in_bytes() == 16);
2541+
match(Set dst (Count$1 src));
2542+
ins_cost(ifelse($1, `TrailingZerosV', `3 * ', `')INSN_COST);
2543+
format %{ "count$1 $dst, $src\t# vector (16B/8H/4S/2D)" %}
2544+
ins_encode %{
2545+
BasicType bt = Matcher::vector_element_basic_type(this);
2546+
Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), true);dnl
2547+
ifelse($1, `TrailingZerosV', `
2548+
__ neon_reverse_bits(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, true);', `')
2549+
if (bt != T_LONG) {
2550+
__ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg));
2551+
} else {
2552+
__ umov(rscratch1, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg), __ D, 0);
2553+
__ clz(rscratch1, rscratch1);
2554+
__ mov(as_FloatRegister($dst$$reg), __ D, 0, rscratch1);
2555+
__ umov(rscratch1, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg), __ D, 1);
2556+
__ clz(rscratch1, rscratch1);
2557+
__ mov(as_FloatRegister($dst$$reg), __ D, 1, rscratch1);
2558+
}
2559+
%}
2560+
ins_pipe(pipe_slow);
2561+
%}')dnl
2562+
dnl
2563+
//------------------------- CountLeadingZerosV -----------------------------
2564+
CLTZ_D(LeadingZerosV)
2565+
CLTZ_X(LeadingZerosV)
2566+
2567+
//------------------------- CountTrailingZerosV ----------------------------
2568+
CLTZ_D(TrailingZerosV)
2569+
CLTZ_X(TrailingZerosV)

‎src/hotspot/cpu/aarch64/aarch64_sve.ad

+67
Original file line numberDiff line numberDiff line change
@@ -5824,3 +5824,70 @@ instruct vmask_gen(pRegGov pg, iRegL len, rFlagsReg cr) %{
58245824
%}
58255825
ins_pipe(pipe_slow);
58265826
%}
5827+
5828+
// ------------------------------ CountLeadingZerosV ------------------------------
5829+
5830+
instruct countLeadingZerosV(vReg dst, vReg src) %{
5831+
predicate(UseSVE > 0 &&
5832+
!n->as_Vector()->is_predicated_vector());
5833+
match(Set dst (CountLeadingZerosV src));
5834+
ins_cost(SVE_COST);
5835+
format %{ "countLeadingZerosV $dst, $src\t# vector (sve)" %}
5836+
ins_encode %{
5837+
BasicType bt = Matcher::vector_element_basic_type(this);
5838+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
5839+
__ sve_clz(as_FloatRegister($dst$$reg), size, ptrue, as_FloatRegister($src$$reg));
5840+
%}
5841+
ins_pipe(pipe_slow);
5842+
%}
5843+
5844+
// The dst and src should use the same register to make sure the
5845+
// inactive lanes in dst save the same elements as src.
5846+
instruct countLeadingZerosV_masked(vReg dst_src, pRegGov pg) %{
5847+
predicate(UseSVE > 0);
5848+
match(Set dst_src (CountLeadingZerosV dst_src pg));
5849+
ins_cost(SVE_COST);
5850+
format %{ "countLeadingZerosV $dst_src, $pg, $dst_src\t# vector (sve)" %}
5851+
ins_encode %{
5852+
BasicType bt = Matcher::vector_element_basic_type(this);
5853+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
5854+
__ sve_clz(as_FloatRegister($dst_src$$reg), size,
5855+
as_PRegister($pg$$reg), as_FloatRegister($dst_src$$reg));
5856+
%}
5857+
ins_pipe(pipe_slow);
5858+
%}
5859+
5860+
// ------------------------------ CountTrailingZerosV -----------------------------
5861+
5862+
instruct countTrailingZerosV(vReg dst, vReg src) %{
5863+
predicate(UseSVE > 0 &&
5864+
!n->as_Vector()->is_predicated_vector());
5865+
match(Set dst (CountTrailingZerosV src));
5866+
ins_cost(2 * SVE_COST);
5867+
format %{ "countTrailingZerosV $dst, $src\t# vector (sve)" %}
5868+
ins_encode %{
5869+
BasicType bt = Matcher::vector_element_basic_type(this);
5870+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
5871+
__ sve_rbit(as_FloatRegister($dst$$reg), size, ptrue, as_FloatRegister($src$$reg));
5872+
__ sve_clz(as_FloatRegister($dst$$reg), size, ptrue, as_FloatRegister($dst$$reg));
5873+
%}
5874+
ins_pipe(pipe_slow);
5875+
%}
5876+
5877+
// The dst and src should use the same register to make sure the
5878+
// inactive lanes in dst save the same elements as src.
5879+
instruct countTrailingZerosV_masked(vReg dst_src, pRegGov pg) %{
5880+
predicate(UseSVE > 0);
5881+
match(Set dst_src (CountTrailingZerosV dst_src pg));
5882+
ins_cost(2 * SVE_COST);
5883+
format %{ "countTrailingZerosV $dst_src, $pg, $dst_src\t# vector (sve)" %}
5884+
ins_encode %{
5885+
BasicType bt = Matcher::vector_element_basic_type(this);
5886+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
5887+
__ sve_rbit(as_FloatRegister($dst_src$$reg), size,
5888+
as_PRegister($pg$$reg), as_FloatRegister($dst_src$$reg));
5889+
__ sve_clz(as_FloatRegister($dst_src$$reg), size,
5890+
as_PRegister($pg$$reg), as_FloatRegister($dst_src$$reg));
5891+
%}
5892+
ins_pipe(pipe_slow);
5893+
%}

‎src/hotspot/cpu/aarch64/aarch64_sve_ad.m4

+51
Original file line numberDiff line numberDiff line change
@@ -3297,3 +3297,54 @@ instruct vmask_gen(pRegGov pg, iRegL len, rFlagsReg cr) %{
32973297
%}
32983298
ins_pipe(pipe_slow);
32993299
%}
3300+
3301+
dnl
3302+
dnl CLTZ($1 )
3303+
dnl CLTZ(op_name)
3304+
define(`CLTZ', `
3305+
instruct count$1(vReg dst, vReg src) %{
3306+
predicate(UseSVE > 0 &&
3307+
!n->as_Vector()->is_predicated_vector());
3308+
match(Set dst (Count$1 src));
3309+
ins_cost(ifelse($1, `TrailingZerosV', `2 * ', `')SVE_COST);
3310+
format %{ "count$1 $dst, $src\t# vector (sve)" %}
3311+
ins_encode %{
3312+
BasicType bt = Matcher::vector_element_basic_type(this);
3313+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);dnl
3314+
ifelse($1, `TrailingZerosV', `
3315+
__ sve_rbit(as_FloatRegister($dst$$reg), size, ptrue, as_FloatRegister($src$$reg));', `')
3316+
__ sve_clz(as_FloatRegister($dst$$reg), size, ptrue, as_FloatRegister($ifelse($1, `LeadingZerosV', src, dst)$$reg));
3317+
%}
3318+
ins_pipe(pipe_slow);
3319+
%}')dnl
3320+
dnl
3321+
dnl
3322+
dnl CLTZ_PREDICATE($1 )
3323+
dnl CLTZ_PREDICATE(op_name)
3324+
define(`CLTZ_PREDICATE', `
3325+
// The dst and src should use the same register to make sure the
3326+
// inactive lanes in dst save the same elements as src.
3327+
instruct count$1_masked(vReg dst_src, pRegGov pg) %{
3328+
predicate(UseSVE > 0);
3329+
match(Set dst_src (Count$1 dst_src pg));
3330+
ins_cost(ifelse($1, `TrailingZerosV', `2 * ', `')SVE_COST);
3331+
format %{ "count$1 $dst_src, $pg, $dst_src\t# vector (sve)" %}
3332+
ins_encode %{
3333+
BasicType bt = Matcher::vector_element_basic_type(this);
3334+
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);dnl
3335+
ifelse($1, `TrailingZerosV', `
3336+
__ sve_rbit(as_FloatRegister($dst_src$$reg), size,
3337+
as_PRegister($pg$$reg), as_FloatRegister($dst_src$$reg));', `')
3338+
__ sve_clz(as_FloatRegister($dst_src$$reg), size,
3339+
as_PRegister($pg$$reg), as_FloatRegister($dst_src$$reg));
3340+
%}
3341+
ins_pipe(pipe_slow);
3342+
%}')dnl
3343+
dnl
3344+
// ------------------------------ CountLeadingZerosV ------------------------------
3345+
CLTZ(LeadingZerosV)
3346+
CLTZ_PREDICATE(LeadingZerosV)
3347+
3348+
// ------------------------------ CountTrailingZerosV -----------------------------
3349+
CLTZ(TrailingZerosV)
3350+
CLTZ_PREDICATE(TrailingZerosV)

‎src/hotspot/cpu/aarch64/assembler_aarch64.hpp

+2
Original file line numberDiff line numberDiff line change
@@ -3046,6 +3046,7 @@ void mvnw(Register Rd, Register Rm,
30463046
INSN(sve_andv, 0b00000100, 0b011010001); // bitwise and reduction to scalar
30473047
INSN(sve_asr, 0b00000100, 0b010000100); // vector arithmetic shift right
30483048
INSN(sve_bic, 0b00000100, 0b011011000); // vector bitwise clear
3049+
INSN(sve_clz, 0b00000100, 0b011001101); // vector count leading zero bits
30493050
INSN(sve_cnt, 0b00000100, 0b011010101); // count non-zero bits
30503051
INSN(sve_cpy, 0b00000101, 0b100000100); // copy scalar to each active vector element
30513052
INSN(sve_eor, 0b00000100, 0b011001000); // vector eor
@@ -3057,6 +3058,7 @@ void mvnw(Register Rd, Register Rm,
30573058
INSN(sve_not, 0b00000100, 0b011110101); // bitwise invert vector, unary
30583059
INSN(sve_orr, 0b00000100, 0b011000000); // vector or
30593060
INSN(sve_orv, 0b00000100, 0b011000001); // bitwise or reduction to scalar
3061+
INSN(sve_rbit, 0b00000101, 0b100111100); // vector reverse bits
30603062
INSN(sve_smax, 0b00000100, 0b001000000); // signed maximum vectors
30613063
INSN(sve_smaxv, 0b00000100, 0b001000001); // signed maximum reduction to scalar
30623064
INSN(sve_smin, 0b00000100, 0b001010000); // signed minimum vectors

‎src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

+26-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -1380,3 +1380,28 @@ void C2_MacroAssembler::sve_compress_byte(FloatRegister dst, FloatRegister src,
13801380
// dst = 00 00 00 88 55 44 22 11
13811381
sve_orr(dst, dst, vtmp1);
13821382
}
1383+
1384+
void C2_MacroAssembler::neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ) {
1385+
assert(bt == T_BYTE || bt == T_SHORT || bt == T_INT || bt == T_LONG, "unsupported basic type");
1386+
SIMD_Arrangement size = isQ ? T16B : T8B;
1387+
switch (bt) {
1388+
case T_BYTE:
1389+
rbit(dst, size, src);
1390+
break;
1391+
case T_SHORT:
1392+
rev16(dst, size, src);
1393+
rbit(dst, size, dst);
1394+
break;
1395+
case T_INT:
1396+
rev32(dst, size, src);
1397+
rbit(dst, size, dst);
1398+
break;
1399+
case T_LONG:
1400+
rev64(dst, size, src);
1401+
rbit(dst, size, dst);
1402+
break;
1403+
default:
1404+
assert(false, "unsupported");
1405+
ShouldNotReachHere();
1406+
}
1407+
}

‎src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -123,4 +123,6 @@
123123
FloatRegister vtmp1, FloatRegister vtmp2,
124124
PRegister pgtmp);
125125

126+
void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
127+
126128
#endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

‎src/hotspot/share/adlc/formssel.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -4238,6 +4238,7 @@ bool MatchRule::is_vector() const {
42384238
"VectorUCastB2X", "VectorUCastS2X", "VectorUCastI2X",
42394239
"VectorMaskWrapper","VectorMaskCmp","VectorReinterpret","LoadVectorMasked","StoreVectorMasked",
42404240
"FmaVD","FmaVF","PopCountVI", "PopCountVL", "VectorLongToMask",
4241+
"CountLeadingZerosV", "CountTrailingZerosV",
42414242
// Next are vector mask ops.
42424243
"MaskAll", "AndVMask", "OrVMask", "XorVMask", "VectorMaskCast",
42434244
// Next are not supported currently.

‎src/hotspot/share/opto/classes.hpp

+2
Original file line numberDiff line numberDiff line change
@@ -153,8 +153,10 @@ macro(LongCountedLoop)
153153
macro(LongCountedLoopEnd)
154154
macro(CountLeadingZerosI)
155155
macro(CountLeadingZerosL)
156+
macro(CountLeadingZerosV)
156157
macro(CountTrailingZerosI)
157158
macro(CountTrailingZerosL)
159+
macro(CountTrailingZerosV)
158160
macro(CreateEx)
159161
macro(DecodeN)
160162
macro(DecodeNKlass)

‎src/hotspot/share/opto/vectornode.cpp

+8
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,12 @@ int VectorNode::opcode(int sopc, BasicType bt) {
240240
return Op_VectorCastF2X;
241241
case Op_ConvD2L:
242242
return Op_VectorCastD2X;
243+
case Op_CountLeadingZerosI:
244+
case Op_CountLeadingZerosL:
245+
return Op_CountLeadingZerosV;
246+
case Op_CountTrailingZerosI:
247+
case Op_CountTrailingZerosL:
248+
return Op_CountTrailingZerosV;
243249

244250
default:
245251
return 0; // Unimplemented
@@ -579,6 +585,8 @@ VectorNode* VectorNode::make(int vopc, Node* n1, Node* n2, const TypeVect* vt, b
579585
case Op_ExpandV: return new ExpandVNode(n1, n2, vt);
580586
case Op_CompressV: return new CompressVNode(n1, n2, vt);
581587
case Op_CompressM: assert(n1 == NULL, ""); return new CompressMNode(n2, vt);
588+
case Op_CountLeadingZerosV: return new CountLeadingZerosVNode(n1, vt);
589+
case Op_CountTrailingZerosV: return new CountTrailingZerosVNode(n1, vt);
582590
default:
583591
fatal("Missed vector creation for '%s'", NodeClassNames[vopc]);
584592
return NULL;

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