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Wang HuangAi Jiaming
Wang Huang
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Ai Jiaming
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8266775: Add VectorLoadConst node implementation for Arm SVE
Co-authored-by: Wang Huang <whuang@openjdk.org> Co-authored-by: Ai Jiaming <aijiaming1@huawei.com> Reviewed-by: xgong, njian
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+42
-12
lines changed

4 files changed

+42
-12
lines changed

src/hotspot/cpu/aarch64/aarch64_neon.ad

+5-4
Original file line numberDiff line numberDiff line change
@@ -3368,9 +3368,10 @@ instruct vmaskcastX(vecX dst)
33683368

33693369
instruct loadcon8B(vecD dst, immI0 src)
33703370
%{
3371-
predicate((n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
3372-
n->as_Vector()->length() == 8) &&
3373-
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3371+
predicate(UseSVE == 0 &&
3372+
(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
3373+
n->as_Vector()->length() == 8) &&
3374+
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
33743375
match(Set dst (VectorLoadConst src));
33753376
ins_cost(INSN_COST);
33763377
format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
@@ -3383,7 +3384,7 @@ instruct loadcon8B(vecD dst, immI0 src)
33833384

33843385
instruct loadcon16B(vecX dst, immI0 src)
33853386
%{
3386-
predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
3387+
predicate(UseSVE == 0 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
33873388
match(Set dst (VectorLoadConst src));
33883389
ins_cost(INSN_COST);
33893390
format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}

src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

+5-4
Original file line numberDiff line numberDiff line change
@@ -1282,10 +1282,11 @@ dnl
12821282
//-------------------------------- LOAD_IOTA_INDICES----------------------------------
12831283
dnl
12841284
define(`PREDICATE', `ifelse($1, 8,
1285-
`predicate((n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
1286-
n->as_Vector()->length() == 8) &&
1287-
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);',
1288-
`predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);')')dnl
1285+
`predicate(UseSVE == 0 &&
1286+
(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
1287+
n->as_Vector()->length() == 8) &&
1288+
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);',
1289+
`predicate(UseSVE == 0 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);')')dnl
12891290
dnl
12901291
define(`VECTOR_LOAD_CON', `
12911292
instruct loadcon$1B`'(vec$2 dst, immI0 src)

src/hotspot/cpu/aarch64/aarch64_sve.ad

+16-2
Original file line numberDiff line numberDiff line change
@@ -225,9 +225,9 @@ source %{
225225
// Others
226226
case Op_ExtractC:
227227
case Op_ExtractUB:
228-
// Vector API specific
229-
case Op_VectorLoadConst:
230228
return false;
229+
// Vector API specific
230+
case Op_LoadVectorGather:
231231
case Op_StoreVectorScatter:
232232
// Currently the implementation for partial vectors are not implemented yet.
233233
// Will add them in a separate patch.
@@ -4219,3 +4219,17 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
42194219
%}
42204220
ins_pipe(pipe_slow);
42214221
%}
4222+
4223+
// ------------------------------ Vector Load Const -------------------------------
4224+
4225+
instruct loadconB(vReg dst, immI0 src) %{
4226+
predicate(UseSVE > 0 &&
4227+
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
4228+
match(Set dst (VectorLoadConst src));
4229+
ins_cost(SVE_COST);
4230+
format %{ "sve_index $dst, 0, 1\t# generate iota indices" %}
4231+
ins_encode %{
4232+
__ sve_index(as_FloatRegister($dst$$reg), __ B, 0, 1);
4233+
%}
4234+
ins_pipe(pipe_slow);
4235+
%}

src/hotspot/cpu/aarch64/aarch64_sve_ad.m4

+16-2
Original file line numberDiff line numberDiff line change
@@ -220,9 +220,9 @@ source %{
220220
// Others
221221
case Op_ExtractC:
222222
case Op_ExtractUB:
223-
// Vector API specific
224-
case Op_VectorLoadConst:
225223
return false;
224+
// Vector API specific
225+
case Op_LoadVectorGather:
226226
case Op_StoreVectorScatter:
227227
// Currently the implementation for partial vectors are not implemented yet.
228228
// Will add them in a separate patch.
@@ -2491,3 +2491,17 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
24912491
%}
24922492
ins_pipe(pipe_slow);
24932493
%}
2494+
2495+
// ------------------------------ Vector Load Const -------------------------------
2496+
2497+
instruct loadconB(vReg dst, immI0 src) %{
2498+
predicate(UseSVE > 0 &&
2499+
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
2500+
match(Set dst (VectorLoadConst src));
2501+
ins_cost(SVE_COST);
2502+
format %{ "sve_index $dst, 0, 1\t# generate iota indices" %}
2503+
ins_encode %{
2504+
__ sve_index(as_FloatRegister($dst$$reg), __ B, 0, 1);
2505+
%}
2506+
ins_pipe(pipe_slow);
2507+
%}

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