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8263348: Add cast nodes from double precision float types to interger… 
… types implementation for Arm SVE

Co-authored-by: Wang Huang <whuang@openjdk.org>
Co-authored-by: He Xuejin <hexuejin2@huawei.com>
Co-authored-by: Ai Jiaming <aijiaming1@huawei.com>
Reviewed-by: njian
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3 people authored and Ningsheng Jian committed Mar 11, 2021
1 parent 78176f7 commit a9c9f75d9bd2add8329552ff0d33aeadec4a1872
Showing 2 changed files with 103 additions and 0 deletions.
74 src/hotspot/cpu/aarch64/aarch64_sve.ad
View file
@@ -2814,6 +2814,19 @@ instruct vcvtFtoI(vReg dst, vReg src)
ins_pipe(pipe_slow);
%}

instruct vcvtDtoL(vReg dst, vReg src)
%{
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (VectorCastD2X src));
ins_cost(SVE_COST);
format %{ "sve_fcvtzs $dst, D, $src, D\t# convert D to L vector" %}
ins_encode %{
__ sve_fcvtzs(as_FloatRegister($dst$$reg), __ D, ptrue, as_FloatRegister($src$$reg), __ D);
%}
ins_pipe(pipe_slow);
%}


instruct vcvtItoD(vReg dst, vReg src)
%{
@@ -2879,6 +2892,24 @@ instruct vcvtFtoS(vReg dst, vReg src, vReg tmp)
ins_pipe(pipe_slow);
%}

instruct vcvtDtoI(vReg dst, vReg src, vReg tmp)
%{
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
n->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (VectorCastD2X src));
effect(TEMP tmp);
ins_cost(3 * SVE_COST);
format %{ "sve_fcvtzs $dst, D, $src, D\n\t"
"sve_dup $tmp, S, 0\n\t"
"sve_uzp1 $dst, S, $dst, tmp\t# convert D to I vector" %}
ins_encode %{
__ sve_fcvtzs(as_FloatRegister($dst$$reg), __ D, ptrue, as_FloatRegister($src$$reg), __ D);
__ sve_dup(as_FloatRegister($tmp$$reg), __ S, 0);
__ sve_uzp1(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
%}
ins_pipe(pipe_slow);
%}



instruct vcvtFtoB(vReg dst, vReg src, vReg tmp)
@@ -2901,6 +2932,26 @@ instruct vcvtFtoB(vReg dst, vReg src, vReg tmp)
ins_pipe(pipe_slow);
%}

instruct vcvtDtoS(vReg dst, vReg src, vReg tmp)
%{
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (VectorCastD2X src));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(4 * SVE_COST);
format %{ "sve_fcvtzs $dst, D, $src, D\n\t"
"sve_dup $tmp, S, 0\n\t"
"sve_uzp1 $dst, S, $dst, tmp\n\t"
"sve_uzp1 $dst, H, $dst, tmp\n\t# convert D to S vector" %}
ins_encode %{
__ sve_fcvtzs(as_FloatRegister($dst$$reg), __ D, ptrue, as_FloatRegister($src$$reg), __ D);
__ sve_dup(as_FloatRegister($tmp$$reg), __ S, 0);
__ sve_uzp1(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
__ sve_uzp1(as_FloatRegister($dst$$reg), __ H, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
%}
ins_pipe(pipe_slow);
%}



instruct vcvtFtoL(vReg dst, vReg src)
@@ -2917,3 +2968,26 @@ instruct vcvtFtoL(vReg dst, vReg src)
%}
ins_pipe(pipe_slow);
%}


instruct vcvtDtoB(vReg dst, vReg src, vReg tmp)
%{
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 8 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorCastD2X src));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(5 * SVE_COST);
format %{ "sve_fcvtzs $dst, D, $src, D\n\t"
"sve_dup $tmp, S, 0\n\t"
"sve_uzp1 $dst, S, $dst, tmp\n\t"
"sve_uzp1 $dst, H, $dst, tmp\n\t"
"sve_uzp1 $dst, B, $dst, tmp\n\t# convert D to B vector" %}
ins_encode %{
__ sve_fcvtzs(as_FloatRegister($dst$$reg), __ D, ptrue, as_FloatRegister($src$$reg), __ D);
__ sve_dup(as_FloatRegister($tmp$$reg), __ S, 0);
__ sve_uzp1(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
__ sve_uzp1(as_FloatRegister($dst$$reg), __ H, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
__ sve_uzp1(as_FloatRegister($dst$$reg), __ B, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
%}
ins_pipe(pipe_slow);
%}
29 src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
View file
@@ -1671,6 +1671,7 @@ dnl $1 $2 $3 $4
VECTOR_CAST_X2X(I, F, scvtf, S)
VECTOR_CAST_X2X(L, D, scvtf, D)
VECTOR_CAST_X2X(F, I, fcvtzs, S)
VECTOR_CAST_X2X(D, L, fcvtzs, D)

dnl
define(`VECTOR_CAST_X2F_EXTEND1', `
@@ -1714,6 +1715,7 @@ instruct vcvt$1to$2`'(vReg dst, vReg src, vReg tmp)
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7
VECTOR_CAST_F2X_NARROW1(F, S, fcvtzs, S, dup, H, uzp1)
VECTOR_CAST_F2X_NARROW1(D, I, fcvtzs, D, dup, S, uzp1)


dnl
@@ -1739,6 +1741,7 @@ instruct vcvt$1to$2`'(vReg dst, vReg src, vReg tmp)
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8
VECTOR_CAST_F2X_NARROW2(F, B, fcvtzs, S, dup, H, uzp1, B)
VECTOR_CAST_F2X_NARROW2(D, S, fcvtzs, D, dup, S, uzp1, H)


dnl
@@ -1759,3 +1762,29 @@ instruct vcvt$1to$2`'(vReg dst, vReg src)
%}')dnl
dnl $1 $2 $3 $4 $5 $6
VECTOR_CAST_F2X_EXTEND1(F, L, fcvtzs, S, sunpklo, D)

dnl
define(`VECTOR_CAST_F2X_NARROW3', `
instruct vcvt$1to$2`'(vReg dst, vReg src, vReg tmp)
%{
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 8 &&
n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (VectorCast$1`'2X src));
effect(TEMP_DEF dst, TEMP tmp);
ins_cost(5 * SVE_COST);
format %{ "sve_$3 $dst, $4, $src, $4\n\t"
"sve_$5 $tmp, $6, 0\n\t"
"sve_$7 $dst, $6, $dst, tmp\n\t"
"sve_$7 $dst, $8, $dst, tmp\n\t"
"sve_$7 $dst, $9, $dst, tmp\n\t# convert $1 to $2 vector" %}
ins_encode %{
__ sve_$3(as_FloatRegister($dst$$reg), __ $4, ptrue, as_FloatRegister($src$$reg), __ $4);
__ sve_$5(as_FloatRegister($tmp$$reg), __ $6, 0);
__ sve_$7(as_FloatRegister($dst$$reg), __ $6, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
__ sve_$7(as_FloatRegister($dst$$reg), __ $8, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
__ sve_$7(as_FloatRegister($dst$$reg), __ $9, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg));
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8 $9
VECTOR_CAST_F2X_NARROW3(D, B, fcvtzs, D, dup, S, uzp1, H, B)

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