8366432: Post-merge aarch64 build fixes

Co-authored-by: Bhavana Kilambi <bkilambi@openjdk.org>
Reviewed-by: xgong

Author: Jatin Bhateja

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -244,6 +244,9 @@ source %{
       case Op_MinVHF:
       case Op_MaxVHF:
       case Op_SqrtVHF:
+      case Op_AbsVHF:
+      case Op_NegVHF:
+      case Op_AddReductionVHF:
         // FEAT_FP16 is enabled if both "fphp" and "asimdhp" features are supported.
         // Only the Neon instructions need this check. SVE supports half-precision floats
         // by default.
@@ -279,20 +282,6 @@ source %{
           return false;
         }
         break;
-      case Op_AddVHF:
-      case Op_SubVHF:
-      case Op_MulVHF:
-      case Op_DivVHF:
-      case Op_AbsVHF:
-      case Op_NegVHF:
-      case Op_FmaVHF:
-      case Op_AddReductionVHF:
-        // FEAT_FP16 is enabled if both "fphp" and "asimdhp" features are supported.
-        // Only the Neon instructions need this check. SVE supports 16-bit floats by default.
-        if (UseSVE > 0 || (VM_Version::supports_fphp() && VM_Version::supports_asimdhp())) {
-          break;
-        }
-        return false;
       default:
         break;
     }

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -234,6 +234,9 @@ source %{
       case Op_MinVHF:
       case Op_MaxVHF:
       case Op_SqrtVHF:
+      case Op_AbsVHF:
+      case Op_NegVHF:
+      case Op_AddReductionVHF:
         // FEAT_FP16 is enabled if both "fphp" and "asimdhp" features are supported.
         // Only the Neon instructions need this check. SVE supports half-precision floats
         // by default.
@@ -269,20 +272,6 @@ source %{
           return false;
         }
         break;
-      case Op_AddVHF:
-      case Op_SubVHF:
-      case Op_MulVHF:
-      case Op_DivVHF:
-      case Op_AbsVHF:
-      case Op_NegVHF:
-      case Op_FmaVHF:
-      case Op_AddReductionVHF:
-        // FEAT_FP16 is enabled if both "fphp" and "asimdhp" features are supported.
-        // Only the Neon instructions need this check. SVE supports 16-bit floats by default.
-        if (UseSVE > 0 || (VM_Version::supports_fphp() && VM_Version::supports_asimdhp())) {
-          break;
-        }
-        return false;
       default:
         break;
     }

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -2068,7 +2068,6 @@ void mvnw(Register Rd, Register Rm,
   void data_processing(unsigned op31, unsigned type, unsigned opcode, unsigned op21,
                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
     starti;
-    int op21 = (opcode == 0b000101) ? 0b0 : 0b1;
     f(op31, 31, 29);
     f(0b11110, 28, 24);
     f(type, 23, 22), f(op21, 21), f(opcode, 15, 10);
@@ -2129,17 +2128,9 @@ void mvnw(Register Rd, Register Rm,
 
   INSN(fabdh, 0b1, 0b1, 0b010); // Floating-point Absolute Difference (half-precision float)
 
-  INSN(fabdh,  0b011, 0b11, 0b000101);
-  INSN(fmulh,  0b000, 0b11, 0b000010);
-  INSN(fdivh,  0b000, 0b11, 0b000110);
-  INSN(faddh,  0b000, 0b11, 0b001010);
-  INSN(fsubh,  0b000, 0b11, 0b001110);
-  INSN(fmaxh,  0b000, 0b11, 0b010010);
-  INSN(fminh,  0b000, 0b11, 0b010110);
-  INSN(fnmulh, 0b000, 0b11, 0b100010);
 #undef INSN
 
-   // Floating-point data-processing (3 source)
+  // Floating-point data-processing (3 source)
   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
                        FloatRegister Va) {