diff --git a/src/hotspot/cpu/aarch64/aarch64_sve.ad b/src/hotspot/cpu/aarch64/aarch64_sve.ad index c3c13b19109..f5683e8adb3 100644 --- a/src/hotspot/cpu/aarch64/aarch64_sve.ad +++ b/src/hotspot/cpu/aarch64/aarch64_sve.ad @@ -2801,6 +2801,19 @@ instruct vcvtLtoD(vReg dst, vReg src) ins_pipe(pipe_slow); %} +instruct vcvtFtoI(vReg dst, vReg src) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_INT); + match(Set dst (VectorCastF2X src)); + ins_cost(SVE_COST); + format %{ "sve_fcvtzs $dst, S, $src, S\t# convert F to I vector" %} + ins_encode %{ + __ sve_fcvtzs(as_FloatRegister($dst$$reg), __ S, ptrue, as_FloatRegister($src$$reg), __ S); + %} + ins_pipe(pipe_slow); +%} + instruct vcvtItoD(vReg dst, vReg src) %{ @@ -2846,3 +2859,61 @@ instruct vcvtFtoD(vReg dst, vReg src) %} ins_pipe(pipe_slow); %} + + +instruct vcvtFtoS(vReg dst, vReg src, vReg tmp) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_SHORT); + match(Set dst (VectorCastF2X src)); + effect(TEMP tmp); + ins_cost(3 * SVE_COST); + format %{ "sve_fcvtzs $dst, S, $src, S\n\t" + "sve_dup $tmp, H, 0\n\t" + "sve_uzp1 $dst, H, $dst, tmp\t# convert F to S vector" %} + ins_encode %{ + __ sve_fcvtzs(as_FloatRegister($dst$$reg), __ S, ptrue, as_FloatRegister($src$$reg), __ S); + __ sve_dup(as_FloatRegister($tmp$$reg), __ H, 0); + __ sve_uzp1(as_FloatRegister($dst$$reg), __ H, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_slow); +%} + + + +instruct vcvtFtoB(vReg dst, vReg src, vReg tmp) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_BYTE); + match(Set dst (VectorCastF2X src)); + effect(TEMP_DEF dst, TEMP tmp); + ins_cost(4 * SVE_COST); + format %{ "sve_fcvtzs $dst, S, $src, S\n\t" + "sve_dup $tmp, H, 0\n\t" + "sve_uzp1 $dst, H, $dst, tmp\n\t" + "sve_uzp1 $dst, B, $dst, tmp\n\t# convert F to B vector" %} + ins_encode %{ + __ sve_fcvtzs(as_FloatRegister($dst$$reg), __ S, ptrue, as_FloatRegister($src$$reg), __ S); + __ sve_dup(as_FloatRegister($tmp$$reg), __ H, 0); + __ sve_uzp1(as_FloatRegister($dst$$reg), __ H, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + __ sve_uzp1(as_FloatRegister($dst$$reg), __ B, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_slow); +%} + + + +instruct vcvtFtoL(vReg dst, vReg src) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_LONG); + match(Set dst (VectorCastF2X src)); + ins_cost(2 * SVE_COST); + format %{ "sve_fcvtzs $dst, S, $src, S\n\t" + "sve_sunpklo $dst, D, $dst\t# convert F to L vector" %} + ins_encode %{ + __ sve_fcvtzs(as_FloatRegister($dst$$reg), __ S, ptrue, as_FloatRegister($src$$reg), __ S); + __ sve_sunpklo(as_FloatRegister($dst$$reg), __ D, as_FloatRegister($dst$$reg)); + %} + ins_pipe(pipe_slow); +%} diff --git a/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 b/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 index 9b6bb9e0453..9027ade4ba9 100644 --- a/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 +++ b/src/hotspot/cpu/aarch64/aarch64_sve_ad.m4 @@ -1654,7 +1654,7 @@ VECTOR_CAST_X2F_NARROW1(L, F, scvtf, S, D, dup, S, uzp1) VECTOR_CAST_X2F_NARROW1(D, F, fcvt, S, D, dup, S, uzp1) dnl -define(`VECTOR_CAST_I2F', ` +define(`VECTOR_CAST_X2X', ` instruct vcvt$1to$2`'(vReg dst, vReg src) %{ predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && @@ -1667,9 +1667,10 @@ instruct vcvt$1to$2`'(vReg dst, vReg src) %} ins_pipe(pipe_slow); %}')dnl -dnl $1 $2 $3 $4 -VECTOR_CAST_I2F(I, F, scvtf, S) -VECTOR_CAST_I2F(L, D, scvtf, D) +dnl $1 $2 $3 $4 +VECTOR_CAST_X2X(I, F, scvtf, S) +VECTOR_CAST_X2X(L, D, scvtf, D) +VECTOR_CAST_X2X(F, I, fcvtzs, S) dnl define(`VECTOR_CAST_X2F_EXTEND1', ` @@ -1691,3 +1692,70 @@ dnl $1 $2 $3 $4 $5 $6 VECTOR_CAST_X2F_EXTEND1(I, D, sunpklo, D, scvtf, D) VECTOR_CAST_X2F_EXTEND1(S, F, sunpklo, S, scvtf, S) VECTOR_CAST_X2F_EXTEND1(F, D, sunpklo, D, fcvt, S) + +dnl +define(`VECTOR_CAST_F2X_NARROW1', ` +instruct vcvt$1to$2`'(vReg dst, vReg src, vReg tmp) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2)); + match(Set dst (VectorCast$1`'2X src)); + effect(TEMP tmp); + ins_cost(3 * SVE_COST); + format %{ "sve_$3 $dst, $4, $src, $4\n\t" + "sve_$5 $tmp, $6, 0\n\t" + "sve_$7 $dst, $6, $dst, tmp\t# convert $1 to $2 vector" %} + ins_encode %{ + __ sve_$3(as_FloatRegister($dst$$reg), __ $4, ptrue, as_FloatRegister($src$$reg), __ $4); + __ sve_$5(as_FloatRegister($tmp$$reg), __ $6, 0); + __ sve_$7(as_FloatRegister($dst$$reg), __ $6, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_slow); +%}')dnl +dnl $1 $2 $3 $4 $5 $6 $7 +VECTOR_CAST_F2X_NARROW1(F, S, fcvtzs, S, dup, H, uzp1) + + +dnl +define(`VECTOR_CAST_F2X_NARROW2', ` +instruct vcvt$1to$2`'(vReg dst, vReg src, vReg tmp) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2)); + match(Set dst (VectorCast$1`'2X src)); + effect(TEMP_DEF dst, TEMP tmp); + ins_cost(4 * SVE_COST); + format %{ "sve_$3 $dst, $4, $src, $4\n\t" + "sve_$5 $tmp, $6, 0\n\t" + "sve_$7 $dst, $6, $dst, tmp\n\t" + "sve_$7 $dst, $8, $dst, tmp\n\t# convert $1 to $2 vector" %} + ins_encode %{ + __ sve_$3(as_FloatRegister($dst$$reg), __ $4, ptrue, as_FloatRegister($src$$reg), __ $4); + __ sve_$5(as_FloatRegister($tmp$$reg), __ $6, 0); + __ sve_$7(as_FloatRegister($dst$$reg), __ $6, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + __ sve_$7(as_FloatRegister($dst$$reg), __ $8, as_FloatRegister($dst$$reg), as_FloatRegister($tmp$$reg)); + %} + ins_pipe(pipe_slow); +%}')dnl +dnl $1 $2 $3 $4 $5 $6 $7 $8 +VECTOR_CAST_F2X_NARROW2(F, B, fcvtzs, S, dup, H, uzp1, B) + + +dnl +define(`VECTOR_CAST_F2X_EXTEND1', ` +instruct vcvt$1to$2`'(vReg dst, vReg src) +%{ + predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 && + n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2)); + match(Set dst (VectorCast$1`'2X src)); + ins_cost(2 * SVE_COST); + format %{ "sve_$3 $dst, $4, $src, $4\n\t" + "sve_$5 $dst, $6, $dst\t# convert $1 to $2 vector" %} + ins_encode %{ + __ sve_$3(as_FloatRegister($dst$$reg), __ $4, ptrue, as_FloatRegister($src$$reg), __ $4); + __ sve_$5(as_FloatRegister($dst$$reg), __ $6, as_FloatRegister($dst$$reg)); + %} + ins_pipe(pipe_slow); +%}')dnl +dnl $1 $2 $3 $4 $5 $6 +VECTOR_CAST_F2X_EXTEND1(F, L, fcvtzs, S, sunpklo, D) diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp index d85d25d9e75..92650006aed 100644 --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp @@ -3452,6 +3452,56 @@ void mvnw(Register Rd, Register Rm, pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0); } +private: + + void encode_fcvtz_T (SIMD_RegVariant T_dst, SIMD_RegVariant T_src, + unsigned& opc, unsigned& opc2) { + assert(T_src != B && T_dst != B && + T_src != Q && T_dst != Q, "invalid register variant"); + if (T_src != D) { + assert(T_src <= T_dst, "invalid register variant"); + } else { + assert(T_dst != H, "invalid register variant"); + } + // In most cases we can treat T_dst,T_src as opc2,opc + // except following four cases. These cases should be converted + // according to Arm's architecture reference manual: + // +-----+------+---+-------------------------------------+ + // | opc | opc2 | U | Instruction Details | + // +-----+------+---+-------------------------------------+ + // | 11 | 10 | 0 | FCVTZS — Single-precision to 64-bit | + // | 11 | 10 | 1 | FCVTZU — Single-precision to 64-bit | + // | 11 | 00 | 0 | FCVTZS — Double-precision to 32-bit | + // | 11 | 00 | 1 | FCVTZU — Double-precision to 32-bit | + // +-----+------+---+-------------------------------------+ + if (T_dst == D && T_src == S) { // Single-precision to 64-bit + T_dst = S; + T_src = D; + } else if (T_dst == S && T_src == D) { // Double-precision to 32-bit + T_dst = B; + T_src = D; + } + opc = T_src; + opc2 = T_dst; + } +public: + +// SVE floating-point convert to integer (predicated) +#define INSN(NAME, sign) \ + void NAME(FloatRegister Zd, SIMD_RegVariant T_dst, PRegister Pg, \ + FloatRegister Zn, SIMD_RegVariant T_src) { \ + starti; \ + unsigned opc, opc2; \ + encode_fcvtz_T(T_dst, T_src, opc, opc2); \ + f(0b01100101, 31, 24), f(opc, 23, 22), f(0b011, 21, 19); \ + f(opc2, 18, 17), f(sign, 16), f(0b101, 15, 13); \ + pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0); \ + } + + INSN(sve_fcvtzs, 0b0); + INSN(sve_fcvtzu, 0b1); +#undef INSN + Assembler(CodeBuffer* code) : AbstractAssembler(code) { } diff --git a/test/hotspot/gtest/aarch64/aarch64-asmtest.py b/test/hotspot/gtest/aarch64/aarch64-asmtest.py index 73409367eaa..3962cea6ba8 100644 --- a/test/hotspot/gtest/aarch64/aarch64-asmtest.py +++ b/test/hotspot/gtest/aarch64/aarch64-asmtest.py @@ -1590,6 +1590,8 @@ def generate(kind, names): ["scvtf", "__ sve_scvtf(z1, __ D, p0, z0, __ S);", "scvtf\tz1.d, p0/m, z0.s"], ["ucvtf", "__ sve_ucvtf(z3, __ D, p1, z2, __ S);", "ucvtf\tz3.d, p1/m, z2.s"], ["fcvt", "__ sve_fcvt(z5, __ D, p3, z4, __ S);", "fcvt\tz5.d, p3/m, z4.s"], + ["fcvtzs", "__ sve_fcvtzs(z19, __ D, p2, z18, __ D);", "fcvtzs\tz19.d, p2/m, z18.d"], + ["fcvtzu", "__ sve_fcvtzu(z19, __ D, p2, z18, __ D);", "fcvtzu\tz19.d, p2/m, z18.d"], ]) print "\n// FloatImmediateOp" diff --git a/test/hotspot/gtest/aarch64/asmtest.out.h b/test/hotspot/gtest/aarch64/asmtest.out.h index 2c96a3f5397..32e9b044b6f 100644 --- a/test/hotspot/gtest/aarch64/asmtest.out.h +++ b/test/hotspot/gtest/aarch64/asmtest.out.h @@ -775,6 +775,8 @@ __ sve_scvtf(z1, __ D, p0, z0, __ S); // scvtf z1.d, p0/m, z0.s __ sve_ucvtf(z3, __ D, p1, z2, __ S); // ucvtf z3.d, p1/m, z2.s __ sve_fcvt(z5, __ D, p3, z4, __ S); // fcvt z5.d, p3/m, z4.s + __ sve_fcvtzs(z19, __ D, p2, z18, __ D); // fcvtzs z19.d, p2/m, z18.d + __ sve_fcvtzu(z19, __ D, p2, z18, __ D); // fcvtzu z19.d, p2/m, z18.d // FloatImmediateOp __ fmovd(v0, 2.0); // fmov d0, #2.0 @@ -980,30 +982,30 @@ 0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061, 0x120cb166, 0x321764bc, 0x52174681, 0x720c0227, 0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01, - 0x14000000, 0x17ffffd7, 0x1400030e, 0x94000000, - 0x97ffffd4, 0x9400030b, 0x3400000a, 0x34fffa2a, - 0x3400610a, 0x35000008, 0x35fff9c8, 0x350060a8, - 0xb400000b, 0xb4fff96b, 0xb400604b, 0xb500001d, - 0xb5fff91d, 0xb5005ffd, 0x10000013, 0x10fff8b3, - 0x10005f93, 0x90000013, 0x36300016, 0x3637f836, - 0x36305f16, 0x3758000c, 0x375ff7cc, 0x37585eac, + 0x14000000, 0x17ffffd7, 0x14000310, 0x94000000, + 0x97ffffd4, 0x9400030d, 0x3400000a, 0x34fffa2a, + 0x3400614a, 0x35000008, 0x35fff9c8, 0x350060e8, + 0xb400000b, 0xb4fff96b, 0xb400608b, 0xb500001d, + 0xb5fff91d, 0xb500603d, 0x10000013, 0x10fff8b3, + 0x10005fd3, 0x90000013, 0x36300016, 0x3637f836, + 0x36305f56, 0x3758000c, 0x375ff7cc, 0x37585eec, 0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc, 0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f, 0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016, 0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0, - 0x54005c80, 0x54000001, 0x54fff541, 0x54005c21, - 0x54000002, 0x54fff4e2, 0x54005bc2, 0x54000002, - 0x54fff482, 0x54005b62, 0x54000003, 0x54fff423, - 0x54005b03, 0x54000003, 0x54fff3c3, 0x54005aa3, - 0x54000004, 0x54fff364, 0x54005a44, 0x54000005, - 0x54fff305, 0x540059e5, 0x54000006, 0x54fff2a6, - 0x54005986, 0x54000007, 0x54fff247, 0x54005927, - 0x54000008, 0x54fff1e8, 0x540058c8, 0x54000009, - 0x54fff189, 0x54005869, 0x5400000a, 0x54fff12a, - 0x5400580a, 0x5400000b, 0x54fff0cb, 0x540057ab, - 0x5400000c, 0x54fff06c, 0x5400574c, 0x5400000d, - 0x54fff00d, 0x540056ed, 0x5400000e, 0x54ffefae, - 0x5400568e, 0x5400000f, 0x54ffef4f, 0x5400562f, + 0x54005cc0, 0x54000001, 0x54fff541, 0x54005c61, + 0x54000002, 0x54fff4e2, 0x54005c02, 0x54000002, + 0x54fff482, 0x54005ba2, 0x54000003, 0x54fff423, + 0x54005b43, 0x54000003, 0x54fff3c3, 0x54005ae3, + 0x54000004, 0x54fff364, 0x54005a84, 0x54000005, + 0x54fff305, 0x54005a25, 0x54000006, 0x54fff2a6, + 0x540059c6, 0x54000007, 0x54fff247, 0x54005967, + 0x54000008, 0x54fff1e8, 0x54005908, 0x54000009, + 0x54fff189, 0x540058a9, 0x5400000a, 0x54fff12a, + 0x5400584a, 0x5400000b, 0x54fff0cb, 0x540057eb, + 0x5400000c, 0x54fff06c, 0x5400578c, 0x5400000d, + 0x54fff00d, 0x5400572d, 0x5400000e, 0x54ffefae, + 0x540056ce, 0x5400000f, 0x54ffef4f, 0x5400566f, 0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60, 0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, 0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200, @@ -1035,7 +1037,7 @@ 0x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176, 0x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422, 0xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a, - 0xbd1b1869, 0x5800467b, 0x1800000b, 0xf8945060, + 0xbd1b1869, 0x580046bb, 0x1800000b, 0xf8945060, 0xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035, 0x3a0700a8, 0x5a0e0367, 0x7a11009b, 0x9a000380, 0xba1e030c, 0xda0f0320, 0xfa030301, 0x0b340b11, @@ -1135,47 +1137,47 @@ 0x05733820, 0x05b238a4, 0x05f138e6, 0x0570396a, 0x25221420, 0x25640461, 0x25a614b2, 0x25eb0553, 0x25221c24, 0x25640c60, 0x25a61cb1, 0x25eb0d52, - 0x65d0a001, 0x65d1a443, 0x65cbac85, 0x1e601000, - 0x1e603000, 0x1e621000, 0x1e623000, 0x1e641000, - 0x1e643000, 0x1e661000, 0x1e663000, 0x1e681000, - 0x1e683000, 0x1e6a1000, 0x1e6a3000, 0x1e6c1000, - 0x1e6c3000, 0x1e6e1000, 0x1e6e3000, 0x1e701000, - 0x1e703000, 0x1e721000, 0x1e723000, 0x1e741000, - 0x1e743000, 0x1e761000, 0x1e763000, 0x1e781000, - 0x1e783000, 0x1e7a1000, 0x1e7a3000, 0x1e7c1000, - 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, 0xf8238358, - 0xf83702af, 0xf8231118, 0xf8392214, 0xf8313022, - 0xf8205098, 0xf82343ec, 0xf83c734a, 0xf82261ec, - 0xf8bf81a1, 0xf8bd0260, 0xf8ac12d1, 0xf8ad23dc, - 0xf8bf3341, 0xf8bc53c4, 0xf8a443c6, 0xf8ba7130, - 0xf8a8600c, 0xf8f48301, 0xf8e20120, 0xf8f8121a, - 0xf8fe2143, 0xf8f7308a, 0xf8f05162, 0xf8e841ea, - 0xf8f17142, 0xf8ec61ec, 0xf86d80e2, 0xf874021a, - 0xf8641082, 0xf86c22b0, 0xf8703170, 0xf8755197, - 0xf87a4397, 0xf86e730b, 0xf86163ec, 0xb82a80f0, - 0xb82201a3, 0xb8331211, 0xb8232161, 0xb83e3105, - 0xb82f53dd, 0xb82040f4, 0xb8347397, 0xb835633b, - 0xb8a582e1, 0xb8b000bf, 0xb8ac1389, 0xb8af22dd, - 0xb8bf33f3, 0xb8a551ee, 0xb8bf4370, 0xb8b47190, - 0xb8ab60c9, 0xb8fe8371, 0xb8fc00fe, 0xb8ea1154, - 0xb8e42238, 0xb8f13076, 0xb8fd52cf, 0xb8f342d3, - 0xb8e270cf, 0xb8ec6170, 0xb86d8037, 0xb87e00b3, - 0xb8711202, 0xb876214d, 0xb875337d, 0xb86c507b, - 0xb861431f, 0xb8737131, 0xb87c61fb, 0xce367a86, - 0xce1e6858, 0xce768d51, 0xce910451, 0xce768338, - 0xce6c8622, 0xcec08363, 0xce708b9d, 0x04e900da, - 0x042404f1, 0x6596012f, 0x65d40b62, 0x65c00745, - 0x0456a72e, 0x04c0175b, 0x04109418, 0x041ab006, - 0x0413812f, 0x04118b65, 0x04101694, 0x04d7aa0a, - 0x045eb046, 0x04c81c5d, 0x044a1dd6, 0x040112fb, - 0x04dcad42, 0x65809aca, 0x658d9603, 0x65c69201, - 0x65878d8c, 0x65c28290, 0x04dda4e5, 0x65c2be0c, - 0x6580a386, 0x65c1a624, 0x658dae6d, 0x65819638, - 0x65f318ca, 0x65a030cd, 0x65a8532e, 0x65bb76d6, - 0x04144e23, 0x04407ce4, 0x04363270, 0x04b6312f, - 0x047e30b9, 0x052b6acd, 0x05b46d0d, 0x041a2c99, - 0x04d828d1, 0x04d93e04, 0x040829da, 0x040a3c6b, - 0x65c73aa1, 0x65c62a2e, 0x65d82678, 0x04c13611, - + 0x65d0a001, 0x65d1a443, 0x65cbac85, 0x65deaa53, + 0x65dfaa53, 0x1e601000, 0x1e603000, 0x1e621000, + 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000, + 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000, + 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000, + 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000, + 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000, + 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, + 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, + 0x1e7e3000, 0xf8238358, 0xf83702af, 0xf8231118, + 0xf8392214, 0xf8313022, 0xf8205098, 0xf82343ec, + 0xf83c734a, 0xf82261ec, 0xf8bf81a1, 0xf8bd0260, + 0xf8ac12d1, 0xf8ad23dc, 0xf8bf3341, 0xf8bc53c4, + 0xf8a443c6, 0xf8ba7130, 0xf8a8600c, 0xf8f48301, + 0xf8e20120, 0xf8f8121a, 0xf8fe2143, 0xf8f7308a, + 0xf8f05162, 0xf8e841ea, 0xf8f17142, 0xf8ec61ec, + 0xf86d80e2, 0xf874021a, 0xf8641082, 0xf86c22b0, + 0xf8703170, 0xf8755197, 0xf87a4397, 0xf86e730b, + 0xf86163ec, 0xb82a80f0, 0xb82201a3, 0xb8331211, + 0xb8232161, 0xb83e3105, 0xb82f53dd, 0xb82040f4, + 0xb8347397, 0xb835633b, 0xb8a582e1, 0xb8b000bf, + 0xb8ac1389, 0xb8af22dd, 0xb8bf33f3, 0xb8a551ee, + 0xb8bf4370, 0xb8b47190, 0xb8ab60c9, 0xb8fe8371, + 0xb8fc00fe, 0xb8ea1154, 0xb8e42238, 0xb8f13076, + 0xb8fd52cf, 0xb8f342d3, 0xb8e270cf, 0xb8ec6170, + 0xb86d8037, 0xb87e00b3, 0xb8711202, 0xb876214d, + 0xb875337d, 0xb86c507b, 0xb861431f, 0xb8737131, + 0xb87c61fb, 0xce367a86, 0xce1e6858, 0xce768d51, + 0xce910451, 0xce768338, 0xce6c8622, 0xcec08363, + 0xce708b9d, 0x04e900da, 0x042404f1, 0x6596012f, + 0x65d40b62, 0x65c00745, 0x0456a72e, 0x04c0175b, + 0x04109418, 0x041ab006, 0x0413812f, 0x04118b65, + 0x04101694, 0x04d7aa0a, 0x045eb046, 0x04c81c5d, + 0x044a1dd6, 0x040112fb, 0x04dcad42, 0x65809aca, + 0x658d9603, 0x65c69201, 0x65878d8c, 0x65c28290, + 0x04dda4e5, 0x65c2be0c, 0x6580a386, 0x65c1a624, + 0x658dae6d, 0x65819638, 0x65f318ca, 0x65a030cd, + 0x65a8532e, 0x65bb76d6, 0x04144e23, 0x04407ce4, + 0x04363270, 0x04b6312f, 0x047e30b9, 0x052b6acd, + 0x05b46d0d, 0x041a2c99, 0x04d828d1, 0x04d93e04, + 0x040829da, 0x040a3c6b, 0x65c73aa1, 0x65c62a2e, + 0x65d82678, 0x04c13611, }; // END Generated code -- do not edit