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Commit e27a878

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Ningsheng Jian
committed
8253211: Make sure jvm does not crash with Arm SVE and Vector API
Reviewed-by: vlivanov
1 parent 925350f commit e27a878

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4 files changed

+133
-7
lines changed

4 files changed

+133
-7
lines changed

‎src/hotspot/cpu/aarch64/aarch64_sve.ad

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,32 @@ source %{
159159
case Op_ExtractL:
160160
case Op_ExtractS:
161161
case Op_ExtractUB:
162+
// Vector API specific
163+
case Op_AndReductionV:
164+
case Op_OrReductionV:
165+
case Op_XorReductionV:
166+
case Op_MaxReductionV:
167+
case Op_MinReductionV:
168+
case Op_LoadVectorGather:
169+
case Op_StoreVectorScatter:
170+
case Op_VectorBlend:
171+
case Op_VectorCast:
172+
case Op_VectorCastB2X:
173+
case Op_VectorCastD2X:
174+
case Op_VectorCastF2X:
175+
case Op_VectorCastI2X:
176+
case Op_VectorCastL2X:
177+
case Op_VectorCastS2X:
178+
case Op_VectorInsert:
179+
case Op_VectorLoadMask:
180+
case Op_VectorLoadShuffle:
181+
case Op_VectorMaskCmp:
182+
case Op_VectorMaskWrapper:
183+
case Op_VectorRearrange:
184+
case Op_VectorReinterpret:
185+
case Op_VectorStoreMask:
186+
case Op_VectorTest:
187+
case Op_VectorUnbox:
162188
return false;
163189
default:
164190
return true;
@@ -846,6 +872,47 @@ instruct vpopcountI(vReg dst, vReg src) %{
846872

847873
// vector add reduction
848874

875+
instruct reduce_addB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
876+
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
877+
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE));
878+
match(Set dst (AddReductionVI src1 src2));
879+
effect(TEMP_DEF dst, TEMP tmp);
880+
ins_cost(SVE_COST);
881+
format %{ "sve_uaddv $tmp, $src2\t# vector (sve) (B)\n\t"
882+
"smov $dst, $tmp, B, 0\n\t"
883+
"addw $dst, $dst, $src1\n\t"
884+
"sxtb $dst, $dst\t # add reduction B" %}
885+
ins_encode %{
886+
__ sve_uaddv(as_FloatRegister($tmp$$reg), __ B,
887+
ptrue, as_FloatRegister($src2$$reg));
888+
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
889+
__ addw($dst$$Register, $dst$$Register, $src1$$Register);
890+
__ sxtb($dst$$Register, $dst$$Register);
891+
%}
892+
ins_pipe(pipe_slow);
893+
%}
894+
895+
instruct reduce_addS(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
896+
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
897+
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
898+
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_CHAR)));
899+
match(Set dst (AddReductionVI src1 src2));
900+
effect(TEMP_DEF dst, TEMP tmp);
901+
ins_cost(SVE_COST);
902+
format %{ "sve_uaddv $tmp, $src2\t# vector (sve) (H)\n\t"
903+
"smov $dst, $tmp, H, 0\n\t"
904+
"addw $dst, $dst, $src1\n\t"
905+
"sxth $dst, $dst\t # add reduction H" %}
906+
ins_encode %{
907+
__ sve_uaddv(as_FloatRegister($tmp$$reg), __ H,
908+
ptrue, as_FloatRegister($src2$$reg));
909+
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
910+
__ addw($dst$$Register, $dst$$Register, $src1$$Register);
911+
__ sxth($dst$$Register, $dst$$Register);
912+
%}
913+
ins_pipe(pipe_slow);
914+
%}
915+
849916
instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegD tmp) %{
850917
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
851918
(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT));

‎src/hotspot/cpu/aarch64/aarch64_sve_ad.m4

Lines changed: 53 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,32 @@ source %{
146146
case Op_ExtractL:
147147
case Op_ExtractS:
148148
case Op_ExtractUB:
149+
// Vector API specific
150+
case Op_AndReductionV:
151+
case Op_OrReductionV:
152+
case Op_XorReductionV:
153+
case Op_MaxReductionV:
154+
case Op_MinReductionV:
155+
case Op_LoadVectorGather:
156+
case Op_StoreVectorScatter:
157+
case Op_VectorBlend:
158+
case Op_VectorCast:
159+
case Op_VectorCastB2X:
160+
case Op_VectorCastD2X:
161+
case Op_VectorCastF2X:
162+
case Op_VectorCastI2X:
163+
case Op_VectorCastL2X:
164+
case Op_VectorCastS2X:
165+
case Op_VectorInsert:
166+
case Op_VectorLoadMask:
167+
case Op_VectorLoadShuffle:
168+
case Op_VectorMaskCmp:
169+
case Op_VectorMaskWrapper:
170+
case Op_VectorRearrange:
171+
case Op_VectorReinterpret:
172+
case Op_VectorStoreMask:
173+
case Op_VectorTest:
174+
case Op_VectorUnbox:
149175
return false;
150176
default:
151177
return true;
@@ -507,8 +533,31 @@ instruct vpopcountI(vReg dst, vReg src) %{
507533
__ sve_cnt(as_FloatRegister($dst$$reg), __ S, ptrue, as_FloatRegister($src$$reg));
508534
%}
509535
ins_pipe(pipe_slow);
510-
%}
536+
%}dnl
511537

538+
dnl
539+
dnl REDUCE_ADD_EXT($1, $2, $3, $4, $5, $6, $7 )
540+
dnl REDUCE_ADD_EXT(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
541+
define(`REDUCE_ADD_EXT', `
542+
instruct $1($3 dst, $4 src1, vReg src2, vRegD tmp) %{
543+
predicate(UseSVE > 0 && n->in(2)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
544+
ELEMENT_SHORT_CHAR($6, n->in(2)));
545+
match(Set dst ($2 src1 src2));
546+
effect(TEMP_DEF dst, TEMP tmp);
547+
ins_cost(SVE_COST);
548+
format %{ "sve_uaddv $tmp, $src2\t# vector (sve) ($5)\n\t"
549+
"smov $dst, $tmp, $5, 0\n\t"
550+
"addw $dst, $dst, $src1\n\t"
551+
"$7 $dst, $dst\t # add reduction $5" %}
552+
ins_encode %{
553+
__ sve_uaddv(as_FloatRegister($tmp$$reg), __ $5,
554+
ptrue, as_FloatRegister($src2$$reg));
555+
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ $5, 0);
556+
__ addw($dst$$Register, $dst$$Register, $src1$$Register);
557+
__ $7($dst$$Register, $dst$$Register);
558+
%}
559+
ins_pipe(pipe_slow);
560+
%}')dnl
512561
dnl
513562
dnl REDUCE_ADD($1, $2, $3, $4, $5, $6, $7 )
514563
dnl REDUCE_ADD(insn_name, op_name, reg_dst, reg_src, size, elem_type, insn1)
@@ -545,8 +594,10 @@ instruct $1($3 src1_dst, vReg src2) %{
545594
%}
546595
ins_pipe(pipe_slow);
547596
%}')dnl
548-
dnl
597+
549598
// vector add reduction
599+
REDUCE_ADD_EXT(reduce_addB, AddReductionVI, iRegINoSp, iRegIorL2I, B, T_BYTE, sxtb)
600+
REDUCE_ADD_EXT(reduce_addS, AddReductionVI, iRegINoSp, iRegIorL2I, H, T_SHORT, sxth)
550601
REDUCE_ADD(reduce_addI, AddReductionVI, iRegINoSp, iRegIorL2I, S, T_INT, addw)
551602
REDUCE_ADD(reduce_addL, AddReductionVL, iRegLNoSp, iRegL, D, T_LONG, add)
552603
REDUCE_ADDF(reduce_addF, AddReductionVF, vRegF, S)

‎src/hotspot/share/opto/output.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -826,9 +826,9 @@ void PhaseOutput::FillLocArray( int idx, MachSafePointNode* sfpt, Node *local,
826826
? Location::int_in_long : Location::normal ));
827827
} else if( t->base() == Type::NarrowOop ) {
828828
array->append(new_loc_value( C->regalloc(), regnum, Location::narrowoop ));
829-
} else if ( t->base() == Type::VectorS || t->base() == Type::VectorD ||
830-
t->base() == Type::VectorX || t->base() == Type::VectorY ||
831-
t->base() == Type::VectorZ) {
829+
} else if (t->base() == Type::VectorA || t->base() == Type::VectorS ||
830+
t->base() == Type::VectorD || t->base() == Type::VectorX ||
831+
t->base() == Type::VectorY || t->base() == Type::VectorZ) {
832832
array->append(new_loc_value( C->regalloc(), regnum, Location::vector ));
833833
} else {
834834
array->append(new_loc_value( C->regalloc(), regnum, C->regalloc()->is_oop(local) ? Location::oop : Location::normal ));

‎src/hotspot/share/opto/vectorIntrinsics.cpp

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -670,7 +670,11 @@ bool LibraryCallKit::inline_vector_mem_operation(bool is_store) {
670670
if (using_byte_array) {
671671
store_num_elem = num_elem * type2aelembytes(elem_bt);
672672
const TypeVect* to_vect_type = TypeVect::make(T_BYTE, store_num_elem);
673-
val = gvn().transform(new VectorReinterpretNode(val, val->bottom_type()->is_vect(), to_vect_type));
673+
if (arch_supports_vector(Op_VectorReinterpret, num_elem, T_BYTE, VecMaskNotUsed)) {
674+
val = gvn().transform(new VectorReinterpretNode(val, val->bottom_type()->is_vect(), to_vect_type));
675+
} else {
676+
return false;
677+
}
674678
}
675679

676680
Node* vstore = gvn().transform(StoreVectorNode::make(0, control(), memory(addr), addr, addr_type, val, store_num_elem));
@@ -682,7 +686,11 @@ bool LibraryCallKit::inline_vector_mem_operation(bool is_store) {
682686
int load_num_elem = num_elem * type2aelembytes(elem_bt);
683687
vload = gvn().transform(LoadVectorNode::make(0, control(), memory(addr), addr, addr_type, load_num_elem, T_BYTE));
684688
const TypeVect* to_vect_type = TypeVect::make(elem_bt, num_elem);
685-
vload = gvn().transform(new VectorReinterpretNode(vload, vload->bottom_type()->is_vect(), to_vect_type));
689+
if (arch_supports_vector(Op_VectorReinterpret, num_elem, T_BYTE, VecMaskNotUsed)) {
690+
vload = gvn().transform(new VectorReinterpretNode(vload, vload->bottom_type()->is_vect(), to_vect_type));
691+
} else {
692+
return false;
693+
}
686694
} else {
687695
// Special handle for masks
688696
if (is_mask) {

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