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8261108: Add cast nodes from integer types to float types implementation for Arm SVE #37

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@@ -2725,12 +2725,11 @@ instruct vcvtBtoD(vReg dst, vReg src)
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
match(Set dst (VectorCastB2X src));
effect(TEMP_DEF dst);
ins_cost(3 * SVE_COST);
ins_cost(4 * SVE_COST);
format %{ "sve_sunpklo $dst, H, $src\n\t"
"sve_sunpklo $dst, S, $dst\n\t"
"sve_sunpklo $dst, D, $dst\n\t"
"sve_D $dst, scvtf, $dst, scvtf\t# convert B to D vector" %}
"sve_scvtf $dst, D, $dst, D\t# convert B to D vector" %}
ins_encode %{
__ sve_sunpklo(as_FloatRegister($dst$$reg), __ H, as_FloatRegister($src$$reg));
__ sve_sunpklo(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($dst$$reg));
@@ -1605,7 +1605,7 @@ instruct vcvt$1to$2`'(vReg dst, vReg src)
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6
dnl $1 $2 $3 $4 $5 $6
VECTOR_CAST_I2F_EXTEND2(B, F, sunpklo, H, S, scvtf)
VECTOR_CAST_I2F_EXTEND2(S, D, sunpklo, S, D, scvtf)

@@ -1616,12 +1616,11 @@ instruct vcvt$1to$2`'(vReg dst, vReg src)
predicate(UseSVE > 0 && n->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (VectorCast$1`'2X src));
effect(TEMP_DEF dst);
ins_cost(3 * SVE_COST);
ins_cost(4 * SVE_COST);
format %{ "sve_$3 $dst, $4, $src\n\t"
"sve_$3 $dst, $5, $dst\n\t"
"sve_$3 $dst, $6, $dst\n\t"
"sve_$6 $dst, $7, $dst, $7\t# convert $1 to $2 vector" %}
"sve_$7 $dst, $6, $dst, $6\t# convert $1 to $2 vector" %}
ins_encode %{
__ sve_$3(as_FloatRegister($dst$$reg), __ $4, as_FloatRegister($src$$reg));
__ sve_$3(as_FloatRegister($dst$$reg), __ $5, as_FloatRegister($dst$$reg));
@@ -1630,7 +1629,7 @@ instruct vcvt$1to$2`'(vReg dst, vReg src)
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7
dnl $1 $2 $3 $4 $5 $6 $7
VECTOR_CAST_I2F_EXTEND3(B, D, sunpklo, H, S, D, scvtf)
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@nsjian

nsjian Feb 18, 2021
Collaborator

Can you please align the comment $1...$7 to the arguments?

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@Wanghuang-Huawei

Wanghuang-Huawei Feb 18, 2021
Author Collaborator

Thank you for your review. I will fix this.


dnl
@@ -1652,7 +1651,7 @@ instruct vcvt$1to$2`'(vReg dst, vReg src, vReg tmp)
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8
dnl $1 $2 $3 $4 $5 $6 $7 $8
VECTOR_CAST_I2F_NARROW1(L, F, scvtf, S, D, dup, S, uzp1)

dnl
@@ -1689,6 +1688,6 @@ instruct vcvt$1to$2`'(vReg dst, vReg src)
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6
dnl $1 $2 $3 $4 $5 $6
VECTOR_CAST_I2F_EXTEND1(I, D, sunpklo, D, scvtf, D)
VECTOR_CAST_I2F_EXTEND1(S, F, sunpklo, S, scvtf, S)
@@ -3353,6 +3353,8 @@ void mvnw(Register Rd, Register Rm,
INSN(sve_whilelsw, 0b111, 0);
#undef INSN

private:

void encode_cvtf_T (SIMD_RegVariant& T_dst, SIMD_RegVariant& T_src) {
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@nsjian

nsjian Feb 18, 2021
Collaborator Outdated

It's better to be a non-public function.

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@Wanghuang-Huawei

Wanghuang-Huawei Feb 18, 2021
Author Collaborator Outdated

Yes, I will fix it.

assert(T_src != B && T_dst != B &&
T_src != Q && T_dst != Q, "invalid register variant");
@@ -3369,6 +3371,8 @@ void mvnw(Register Rd, Register Rm,
T_src = B;
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@nsjian

nsjian Feb 19, 2021
Collaborator

This looks confusing. I understand that it's just 0b00, but using B here is really confusing. Maybe using 0b00 and 0b11 directly to align with Arm ARM opc/opc2?

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@Wanghuang-Huawei

Wanghuang-Huawei Feb 19, 2021
Author Collaborator

Arm uses confusing encoding . If we use 0b00 / 0b11 , we can not get a concise macroassmbler here ( for example. other developers can not use this macro). In fact, gcc uses switch..case to convert macro assmbler into Arm's funny encoding.

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@Wanghuang-Huawei

Wanghuang-Huawei Feb 19, 2021
Author Collaborator

If we use an encoding function (like switch..case in gcc) instead of convert function(encode_cvtf_T), source codes here will be a little complicated. :-)

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@XiaohongGong

XiaohongGong Feb 20, 2021
Collaborator

I agree with @nsjian that swapping "T_dst" and "T_src" is confusing although this can generate the same final result. As I understand that this function is used to generate two opcs from the dst and src type, I'd like not using the swap logic. Thanks!

}
}
public:

// SVE convert integer to floating-point (predicated)
#define INSN(NAME, sign) \
void NAME(FloatRegister Zd, SIMD_RegVariant T_dst, PRegister Pg, \