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8266775: Add VectorLoadConst node implementation for Arm SVE #79

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@@ -3368,9 +3368,10 @@ instruct vmaskcastX(vecX dst)

instruct loadcon8B(vecD dst, immI0 src)
%{
predicate((n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8) &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
predicate(UseSVE == 0 &&
(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8) &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorLoadConst src));
ins_cost(INSN_COST);
format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
@@ -3383,7 +3384,7 @@ instruct loadcon8B(vecD dst, immI0 src)

instruct loadcon16B(vecX dst, immI0 src)
%{
predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
predicate(UseSVE == 0 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorLoadConst src));
ins_cost(INSN_COST);
format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
@@ -1282,10 +1282,11 @@ dnl
//-------------------------------- LOAD_IOTA_INDICES----------------------------------
dnl
define(`PREDICATE', `ifelse($1, 8,
`predicate((n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8) &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);',
`predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);')')dnl
`predicate(UseSVE == 0 &&
(n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
n->as_Vector()->length() == 8) &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);',
`predicate(UseSVE == 0 && n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);')')dnl
dnl
define(`VECTOR_LOAD_CON', `
instruct loadcon$1B`'(vec$2 dst, immI0 src)
@@ -225,9 +225,9 @@ source %{
// Others
case Op_ExtractC:
case Op_ExtractUB:
// Vector API specific
case Op_VectorLoadConst:
return false;
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
// Currently the implementation for partial vectors are not implemented yet.
// Will add them in a separate patch.
@@ -4219,3 +4219,17 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Const -------------------------------

instruct loadconB(vReg dst, immI0 src) %{
predicate(UseSVE > 0 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorLoadConst src));
ins_cost(SVE_COST);
format %{ "sve_index $dst, 0, 1\t# generate iota indices" %}
ins_encode %{
__ sve_index(as_FloatRegister($dst$$reg), __ B, 0, 1);
%}
ins_pipe(pipe_slow);
%}
@@ -220,9 +220,9 @@ source %{
// Others
case Op_ExtractC:
case Op_ExtractUB:
// Vector API specific
case Op_VectorLoadConst:
return false;
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
// Currently the implementation for partial vectors are not implemented yet.
// Will add them in a separate patch.
@@ -2491,3 +2491,17 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Const -------------------------------

instruct loadconB(vReg dst, immI0 src) %{
predicate(UseSVE > 0 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
Comment on lines +2498 to +2499

This comment has been minimized.

@nsjian

nsjian May 12, 2021
Collaborator

When the size is 16, the neon pattern will also be matched. Can you please add "UseSVE == 0" for NEON VectorLoadConst patterns?

This comment has been minimized.

@Wanghuang-Huawei

Wanghuang-Huawei May 12, 2021
Author Collaborator

Thank you for your review. I have changed that.

match(Set dst (VectorLoadConst src));
ins_cost(SVE_COST);
format %{ "sve_index $dst, 0, 1\t# generate iota indices" %}
ins_encode %{
__ sve_index(as_FloatRegister($dst$$reg), __ B, 0, 1);
%}
ins_pipe(pipe_slow);
%}