Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

8266775: Add VectorLoadConst node implementation for Arm SVE #79

Closed
Closed
Changes from 3 commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
@@ -225,9 +225,9 @@ source %{
// Others
case Op_ExtractC:
case Op_ExtractUB:
// Vector API specific
case Op_VectorLoadConst:
return false;
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
// Currently the implementation for partial vectors are not implemented yet.
// Will add them in a separate patch.
@@ -4219,3 +4219,17 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Const -------------------------------
instruct loadconB(vReg dst, immI0 src)
%{
predicate(UseSVE > 0 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorLoadConst src));
ins_cost(SVE_COST);
format %{ "sve_index $dst, 0, 1\t# generate iota indices" %}
ins_encode %{
__ sve_index(as_FloatRegister($dst$$reg), __ B, 0, 1);
%}
ins_pipe(pipe_slow);
%}
@@ -220,9 +220,9 @@ source %{
// Others
case Op_ExtractC:
case Op_ExtractUB:
// Vector API specific
case Op_VectorLoadConst:
return false;
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
// Currently the implementation for partial vectors are not implemented yet.
// Will add them in a separate patch.
@@ -2491,3 +2491,17 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Const -------------------------------
instruct loadconB(vReg dst, immI0 src)
Copy link
Collaborator

@nsjian nsjian May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Add a blank line between them?

Copy link
Collaborator Author

@Wanghuang-Huawei Wanghuang-Huawei May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sure.

%{
predicate(UseSVE > 0 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
Copy link
Collaborator

@nsjian nsjian May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

When the size is 16, the neon pattern will also be matched. Can you please add "UseSVE == 0" for NEON VectorLoadConst patterns?

Copy link
Collaborator Author

@Wanghuang-Huawei Wanghuang-Huawei May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thank you for your review. I have changed that.

match(Set dst (VectorLoadConst src));
ins_cost(SVE_COST);
format %{ "sve_index $dst, 0, 1\t# generate iota indices" %}
ins_encode %{
__ sve_index(as_FloatRegister($dst$$reg), __ B, 0, 1);
%}
ins_pipe(pipe_slow);
%}