Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

8266775: Add VectorLoadConst node implementation for Arm SVE #79

Closed
wants to merge 5 commits into from
+42 −12
Closed

8266775: Add VectorLoadConst node implementation for Arm SVE #79

Changes from 2 commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
b8b662d
8266775: Add VectorLoadConst node implementation for Arm SVE
May 8, 2021
ad86b7a
fix cost
May 8, 2021
06f3b97
use sve_index
May 11, 2021
9c7f930
trivial fix
May 12, 2021
c26e5dd
add blank line
May 14, 2021
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
19 src/hotspot/cpu/aarch64/aarch64_sve.ad
View file
Open in desktop
@@ -225,9 +225,9 @@ source %{
// Others
case Op_ExtractC:
case Op_ExtractUB:
// Vector API specific
case Op_VectorLoadConst:
return false;
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
// Currently the implementation for partial vectors are not implemented yet.
// Will add them in a separate patch.
@@ -4219,3 +4219,18 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Const -------------------------------
instruct loadconB(vReg dst, immI0 src)
%{
predicate(UseSVE > 0 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorLoadConst src));
ins_cost(INSN_COST + SVE_COST);
format %{ "sve_ld1b $dst, CONSTANT_MEMORY\t# load iota indices" %}
ins_encode %{
__ lea(rscratch1, ExternalAddress(StubRoutines::aarch64::vector_iota_indices()));
__ sve_ld1b(as_FloatRegister($dst$$reg), __ B, ptrue, Address(rscratch1, 0));
Copy link
Collaborator

@XiaohongGong XiaohongGong May 10, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Could it use INDEX <Zd>.<T>, #<imm1>, #<imm2> (Create index starting from and incremented by immediate) here?

Copy link
Collaborator Author

@Wanghuang-Huawei Wanghuang-Huawei May 11, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Great suggestion. I will change that. Thank you.

%}
ins_pipe(pipe_slow);
%}
19 src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
View file
Open in desktop
@@ -220,9 +220,9 @@ source %{
// Others
case Op_ExtractC:
case Op_ExtractUB:
// Vector API specific
case Op_VectorLoadConst:
return false;
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
// Currently the implementation for partial vectors are not implemented yet.
// Will add them in a separate patch.
@@ -2491,3 +2491,18 @@ instruct scatterL(vmemA mem, vReg src, vReg idx) %{
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Const -------------------------------
instruct loadconB(vReg dst, immI0 src)
Copy link
Collaborator

@nsjian nsjian May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Add a blank line between them?

Copy link
Collaborator Author

@Wanghuang-Huawei Wanghuang-Huawei May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sure.

%{
predicate(UseSVE > 0 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
Copy link
Collaborator

@nsjian nsjian May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

When the size is 16, the neon pattern will also be matched. Can you please add "UseSVE == 0" for NEON VectorLoadConst patterns?

Copy link
Collaborator Author

@Wanghuang-Huawei Wanghuang-Huawei May 12, 2021

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thank you for your review. I have changed that.

match(Set dst (VectorLoadConst src));
ins_cost(INSN_COST + SVE_COST);
format %{ "sve_ld1b $dst, CONSTANT_MEMORY\t# load iota indices" %}
ins_encode %{
__ lea(rscratch1, ExternalAddress(StubRoutines::aarch64::vector_iota_indices()));
__ sve_ld1b(as_FloatRegister($dst$$reg), __ B, ptrue, Address(rscratch1, 0));
%}
ins_pipe(pipe_slow);
%}
14 src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp
View file
Open in desktop
@@ -622,6 +622,20 @@ class StubGenerator: public StubCodeGenerator {
address start = __ pc();
__ emit_data64(0x0706050403020100, relocInfo::none);
__ emit_data64(0x0F0E0D0C0B0A0908, relocInfo::none);
__ emit_data64(0x1716151413121110, relocInfo::none);
__ emit_data64(0x1F1E1D1C1B1A1918, relocInfo::none);
__ emit_data64(0x2726252423222120, relocInfo::none);
__ emit_data64(0x2F2E2D2C2B2A2928, relocInfo::none);
__ emit_data64(0x3736353433323130, relocInfo::none);
__ emit_data64(0x3F3E3D3C3B3A3938, relocInfo::none);
__ emit_data64(0x4746454443424140, relocInfo::none);
__ emit_data64(0x4F4E4D4C4B4A4948, relocInfo::none);
__ emit_data64(0x5756555453525150, relocInfo::none);
__ emit_data64(0x5F5E5D5C5B5A5958, relocInfo::none);
__ emit_data64(0x6766656463626160, relocInfo::none);
__ emit_data64(0x6F6E6D6C6B6A6968, relocInfo::none);
__ emit_data64(0x7776757473727170, relocInfo::none);
__ emit_data64(0x7F7E7D7C7B7A7978, relocInfo::none);
return start;
}