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[vector] Removing generic operand related changes, these will not be …

…merged through

 mainline patches for JDK-8230015, JDK-8234391, JDK-8234392 and JDK-8234394 once they are
 reviewed by community.
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jatin-bhateja authored and Jatin Bhateja committed Nov 22, 2019
1 parent 4c1156f commit 50726e922bab01766162bdc1e28fc0a97725d3f0

This file was deleted.

@@ -1097,13 +1097,6 @@ reg_class vectorz_reg_legacy(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0
reg_class_dynamic vectorz_reg(vectorz_reg_evex, vectorz_reg_legacy, %{ VM_Version::supports_evex() %} );
reg_class_dynamic vectorz_reg_vl(vectorz_reg_evex, vectorz_reg_legacy, %{ VM_Version::supports_evex() && VM_Version::supports_avx512vl() %} );

// Dummy register class
reg_class_dynamic vector_reg(vectory_reg, vectorx_reg, %{ VM_Version::supports_avxonly() %} );
reg_class_dynamic vectorg_reg(vectorz_reg_evex, vector_reg, %{ VM_Version::supports_evex() %} );




reg_class xmm0_reg(XMM0, XMM0b, XMM0c, XMM0d);
reg_class ymm0_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h);
reg_class zmm0_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, XMM0i, XMM0j, XMM0k, XMM0l, XMM0m, XMM0n, XMM0o, XMM0p);
@@ -1309,8 +1302,6 @@ class HandlerImpl {
source %{

#include "opto/addnode.hpp"
#include "utilities/pair.hpp"


// Emit exception handler code.
// Stuff framesize into a register and call a VM stub routine.
@@ -1401,25 +1392,6 @@ int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
static address vector_short_to_byte_mask() { return StubRoutines::x86::vector_short_to_byte_mask(); }

//=============================================================================

static inline int GetVectorLengthEnc(const Node *n ) {
const TypeVect * vt = n->bottom_type()->is_vect();
switch(vt->length_in_bytes()) {
default:
assert(0 , "Incorrect vector type");
case 4:
case 8:
case 16:
return 0;
case 32:
return 1;
case 64:
return 2;
}
return -1;
}


const bool Matcher::match_rule_supported(int opcode) {
if (!has_match_rule(opcode))
return false;
@@ -2189,12 +2161,6 @@ static inline jlong replicate8_imm(int con, int width) {
return val;
}

static inline jlong replicate_imm(int con, int width, int vl) {
if (vl == 4)
return (jlong)replicate4_imm(con, width);
else
return (jlong)replicate8_imm(con, width);
}

#ifndef PRODUCT
void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
@@ -3159,22 +3125,6 @@ instruct fmaF_reg(regF a, regF b, regF c) %{
%}

// ====================VECTOR INSTRUCTIONS=====================================
instruct MoveLegVecG2VecG(vecG dst, legVecG src) %{
match(Set dst src);
format %{ "Dummy moves" %}
ins_encode %{
%}
ins_pipe( fpu_reg_reg );
%}

instruct MoveVecG2LegVecG(legVecG dst, vecG src) %{
match(Set dst src);
format %{ "Dummy moves" %}
ins_encode %{
%}
ins_pipe( fpu_reg_reg );
%}


instruct reinterpretS(vecS dst) %{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 4 && n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 4);
%}
ins_pipe( pipe_slow );
%}

instruct vpopcount4I(vecX dst, vecX src) %{
predicate(VM_Version::supports_vpopcntdq() && UsePopCountInstruction && n->as_Vector()->length() == 4);
match(Set dst (PopCountVI src));
@@ -3353,31 +3353,6 @@ ins_attrib ins_alignment(1); // Required alignment attribute (must be a power
// instruction definitions.

//----------Simple Operands----------------------------------------------------
// Generic vector operands.
operand vecG() %{
constraint(ALLOC_IN_RC(vectorg_reg));
match(VecX);
match(VecY);
match(VecZ);
match(VecS);
match(VecD);

format %{ %}
interface(REG_INTER);
%}

operand legVecG() %{
constraint(ALLOC_IN_RC(vectorg_reg));
match(VecX);
match(VecY);
match(VecZ);
match(VecS);
match(VecD);

format %{ %}
interface(REG_INTER);
%}

// Immediate Operands
// Integer Immediate
operand immI() %{
@@ -2884,7 +2884,7 @@ frame
RAX_H_num // Op_RegL
};
// Excluded flags and vector registers.
assert(ARRAY_SIZE(hi) == _last_machine_leaf - 7, "missing type");
assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
%}
%}
@@ -3704,32 +3704,6 @@ operand vlRegD() %{
interface(REG_INTER);
%}

// Generic vector operands.
operand vecG() %{
constraint(ALLOC_IN_RC(vectorg_reg));
match(VecX);
match(VecY);
match(VecZ);
match(VecS);
match(VecD);

format %{ %}
interface(REG_INTER);
%}

operand legVecG() %{
constraint(ALLOC_IN_RC(vectorg_reg));
match(VecX);
match(VecY);
match(VecZ);
match(VecS);
match(VecD);

format %{ %}
interface(REG_INTER);
%}


// Vectors
operand vecS() %{
constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
@@ -273,23 +273,8 @@ void ArchDesc::inspectOperands() {
const char *result = op->reduce_result();
bool has_root = false;

// Currently operand clause having multiple match rules only
// accept one primary operand(e.g. VecX/VecY/VecG/RegI etc.)
// and other matches are against operand clauses.
// Extending multi-match scenarios in operand clause to accommodate
// multiple primary operands.
if (strcmp(rootOp,"vecG")==0 || strcmp(rootOp,"legVecG")==0) {
MatchRule * rule = &mrule;
while(rule) {
rule->_machType = rootOp;
buildMatchList(rule, result, rootOp, pred, cost);
rule = rule->_next;
}
} else {
// Construct a MatchList for this entry
buildMatchList(op->_matrule, result, rootOp, pred, cost);
}

// Construct a MatchList for this entry
buildMatchList(op->_matrule, result, rootOp, pred, cost);
}
}

@@ -881,12 +866,6 @@ const char *ArchDesc::reg_mask(InstructForm &inForm) {
abort();
}

// For generic registers operands, pull the register mask
// of its dst operands
if (strcmp(result, "vecG")==0 || strcmp(result, "legVecG")==0 ) {
return "*(this->_opnds[0]->in_RegMask(0))";
}

// Instructions producing 'Universe' use RegMask::Empty
if( strcmp(result,"Universe")==0 ) {
return "RegMask::Empty";
@@ -955,7 +934,6 @@ const char *ArchDesc::getIdealType(const char *idealOp) {
case 'X': return "TypeVect::VECTX";
case 'Y': return "TypeVect::VECTY";
case 'Z': return "TypeVect::VECTZ";
case 'G': return "TypeVect::VECTG";
default:
internal_err("Vector type %s with unrecognized type\n",idealOp);
}
@@ -3960,7 +3960,6 @@ bool MatchRule::is_base_register(FormDict &globals) const {
strcmp(opType,"VecX")==0 ||
strcmp(opType,"VecY")==0 ||
strcmp(opType,"VecZ")==0 ||
strcmp(opType,"VecG")==0 ||
strcmp(opType,"Reg" )==0) ) {
return 1;
}
@@ -1577,9 +1577,6 @@ void ArchDesc::declareClasses(FILE *fp) {
fprintf(fp," assert(operand_index < _num_opnds, \"invalid _opnd_array index\");\n");
fprintf(fp," _opnd_array[operand_index] = operand;\n");
fprintf(fp," }\n");
fprintf(fp," virtual uint rule() const { return %s_rule; }\n",
instr->_ident);

fprintf(fp,"private:\n");
if ( instr->is_ideal_jump() ) {
fprintf(fp," virtual void add_case_label(int index_num, Label* blockLabel) {\n");
@@ -1591,6 +1588,8 @@ void ArchDesc::declareClasses(FILE *fp) {
}

out_RegMask(fp); // output register mask
fprintf(fp," virtual uint rule() const { return %s_rule; }\n",
instr->_ident);

// If this instruction contains a labelOper
// Declare Node::methods that set operand Label's contents
@@ -1900,42 +1899,24 @@ void ArchDesc::declareClasses(FILE *fp) {
// as is done for pointers
//
// Construct appropriate constant type containing the constant value.
bool isVector = false;
OperandForm * output = (OperandForm*)(instr->_localNames[instr->_parameters.name(0)]);
if (output) {
const char * outputOperand = output->_ident;
isVector = 0 == strcmp(outputOperand, "vecG") || 0 == strcmp(outputOperand, "legVecG");
}
fprintf(fp," virtual const class Type *bottom_type() const {\n");
switch( data_type ) {
case Form::idealI:
if (isVector)
fprintf(fp," return TypeVect::VECTS;\n");
else
fprintf(fp," return TypeInt::make(opnd_array(1)->constant());\n");
fprintf(fp," return TypeInt::make(opnd_array(1)->constant());\n");
break;
case Form::idealP:
case Form::idealN:
case Form::idealNKlass:
fprintf(fp," return opnd_array(1)->type();\n");
break;
case Form::idealD:
if (isVector)
fprintf(fp," return TypeVect::VECTD;\n");
else
fprintf(fp," return TypeD::make(opnd_array(1)->constantD());\n");
fprintf(fp," return TypeD::make(opnd_array(1)->constantD());\n");
break;
case Form::idealF:
if (isVector)
fprintf(fp," return TypeVect::VECTS;\n");
else
fprintf(fp," return TypeF::make(opnd_array(1)->constantF());\n");
fprintf(fp," return TypeF::make(opnd_array(1)->constantF());\n");
break;
case Form::idealL:
if (isVector)
fprintf(fp," return TypeVect::VECTD;\n");
else
fprintf(fp," return TypeLong::make(opnd_array(1)->constantL());\n");
fprintf(fp," return TypeLong::make(opnd_array(1)->constantL());\n");
break;
default:
assert( false, "Unimplemented()" );
@@ -160,9 +160,6 @@ void C2Compiler::compile_method(ciEnv* env, ciMethod* target, int entry_bci, Dir

void C2Compiler::print_timers() {
Compile::print_timers();
#ifdef X86
tty->print_cr(" Vector Node Count: %d", Compile::_vec_nodes);
#endif
}

bool C2Compiler::is_intrinsic_supported(const methodHandle& method, bool is_virtual) {
@@ -171,7 +171,6 @@ CallGenerator* Compile::find_intrinsic(ciMethod* m, bool is_virtual) {
// in library_call.cpp.


int Compile::_vec_nodes = 0;
#ifndef PRODUCT
// statistics gathering...

@@ -2948,16 +2947,8 @@ void Compile::Code_Gen() {
{
TracePhase tp("matcher", &timers[_t_matcher]);
matcher.match();
print_method(PHASE_AFTER_MATCHING, 3);
}

#ifdef X86
{
TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]);
matcher.do_post_selection_processing(this, root());
}
#endif
print_method(PHASE_AFTER_MATCHING, 3);

// In debug mode can dump m._nodes.dump() for mapping of ideal to machine
// nodes. Mapping is only valid at the root of each matched subtree.
NOT_PRODUCT( verify_graph_edges(); )
@@ -172,7 +172,6 @@ class Compile : public Phase {
friend class VMStructs;

public:
static int _vec_nodes;
// Fixed alias indexes. (See also MergeMemNode.)
enum {
AliasIdxTop = 1, // pseudo-index, aliases to nothing (used as sentinel value)
@@ -241,9 +241,6 @@ class MachNode : public Node {
int operand_index(uint operand) const;
int operand_index(const MachOper *oper) const;

virtual int oprnd_index(int param_index) const {return -1;}


// Register class input is expected in
virtual const RegMask &in_RegMask(uint) const;

@@ -1032,8 +1029,7 @@ class MachTempNode : public MachNode {

public:
virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); }
virtual uint rule() const { return 9999998; }

virtual uint rule() const { return 9999999; }
virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {}

MachTempNode(MachOper* oper) {

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