Skip to content

Commit

Permalink
8283865: riscv: Break down -XX:+UseRVB into seperate options for each…
Browse files Browse the repository at this point in the history 
… bitmanip extension

Reviewed-by: fyang
Backport-of: 060a1887339a366075755ad2a359ee3336ef381d
  • Loading branch information
@zifeihan @RealFYang
zifeihan authored and RealFYang committed Mar 26, 2024
1 parent 8aa0808 commit aee4eea
Show file tree
Hide file tree
Showing 8 changed files with 112 additions and 118 deletions.
1 change: 1 addition & 0 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1945,6 +1945,7 @@ enum Nf {

// ====================================
// RISC-V Bit-Manipulation Extension
// Currently only support Zba and Zbb.
// ====================================
#define INSN(NAME, op, funct3, funct7) \
void NAME(Register Rd, Register Rs1, Register Rs2) { \
Expand Down
3 changes: 2 additions & 1 deletion src/hotspot/cpu/riscv/globals_riscv.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,8 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, AvoidUnalignedAccesses, true, \
"Avoid generating unaligned memory accesses") \
experimental(bool, UseRVV, false, "Use RVV instructions") \
experimental(bool, UseRVB, false, "Use RVB instructions") \
experimental(bool, UseZba, false, "Use Zba instructions") \
experimental(bool, UseZbb, false, "Use Zbb instructions") \
experimental(bool, UseRVC, false, "Use RVC instructions")

#endif // CPU_RISCV_GLOBALS_RISCV_HPP
44 changes: 22 additions & 22 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1426,7 +1426,7 @@ void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in
// reverse bytes in halfword in lower 16 bits and sign-extend
// Rd[15:0] = Rs[7:0] Rs[15:8] (sign-extend to 64 bits)
void MacroAssembler::revb_h_h(Register Rd, Register Rs, Register tmp) {
if (UseRVB) {
if (UseZbb) {
rev8(Rd, Rs);
srai(Rd, Rd, 48);
return;
Expand All @@ -1443,7 +1443,7 @@ void MacroAssembler::revb_h_h(Register Rd, Register Rs, Register tmp) {
// reverse bytes in lower word and sign-extend
// Rd[31:0] = Rs[7:0] Rs[15:8] Rs[23:16] Rs[31:24] (sign-extend to 64 bits)
void MacroAssembler::revb_w_w(Register Rd, Register Rs, Register tmp1, Register tmp2) {
if (UseRVB) {
if (UseZbb) {
rev8(Rd, Rs);
srai(Rd, Rd, 32);
return;
Expand All @@ -1460,7 +1460,7 @@ void MacroAssembler::revb_w_w(Register Rd, Register Rs, Register tmp1, Register
// reverse bytes in halfword in lower 16 bits and zero-extend
// Rd[15:0] = Rs[7:0] Rs[15:8] (zero-extend to 64 bits)
void MacroAssembler::revb_h_h_u(Register Rd, Register Rs, Register tmp) {
if (UseRVB) {
if (UseZbb) {
rev8(Rd, Rs);
srli(Rd, Rd, 48);
return;
Expand All @@ -1477,11 +1477,11 @@ void MacroAssembler::revb_h_h_u(Register Rd, Register Rs, Register tmp) {
// reverse bytes in halfwords in lower 32 bits and zero-extend
// Rd[31:0] = Rs[23:16] Rs[31:24] Rs[7:0] Rs[15:8] (zero-extend to 64 bits)
void MacroAssembler::revb_h_w_u(Register Rd, Register Rs, Register tmp1, Register tmp2) {
if (UseRVB) {
if (UseZbb) {
rev8(Rd, Rs);
rori(Rd, Rd, 32);
roriw(Rd, Rd, 16);
zext_w(Rd, Rd);
zero_extend(Rd, Rd, 32);
return;
}
assert_different_registers(Rs, tmp1, tmp2);
Expand Down Expand Up @@ -1510,16 +1510,16 @@ void MacroAssembler::revb_h_helper(Register Rd, Register Rs, Register tmp1, Regi
// reverse bytes in each halfword
// Rd[63:0] = Rs[55:48] Rs[63:56] Rs[39:32] Rs[47:40] Rs[23:16] Rs[31:24] Rs[7:0] Rs[15:8]
void MacroAssembler::revb_h(Register Rd, Register Rs, Register tmp1, Register tmp2) {
if (UseRVB) {
if (UseZbb) {
assert_different_registers(Rs, tmp1);
assert_different_registers(Rd, tmp1);
rev8(Rd, Rs);
zext_w(tmp1, Rd);
zero_extend(tmp1, Rd, 32);
roriw(tmp1, tmp1, 16);
slli(tmp1, tmp1, 32);
srli(Rd, Rd, 32);
roriw(Rd, Rd, 16);
zext_w(Rd, Rd);
zero_extend(Rd, Rd, 32);
orr(Rd, Rd, tmp1);
return;
}
Expand All @@ -1534,7 +1534,7 @@ void MacroAssembler::revb_h(Register Rd, Register Rs, Register tmp1, Register tm
// reverse bytes in each word
// Rd[63:0] = Rs[39:32] Rs[47:40] Rs[55:48] Rs[63:56] Rs[7:0] Rs[15:8] Rs[23:16] Rs[31:24]
void MacroAssembler::revb_w(Register Rd, Register Rs, Register tmp1, Register tmp2) {
if (UseRVB) {
if (UseZbb) {
rev8(Rd, Rs);
rori(Rd, Rd, 32);
return;
Expand All @@ -1548,7 +1548,7 @@ void MacroAssembler::revb_w(Register Rd, Register Rs, Register tmp1, Register tm
// reverse bytes in doubleword
// Rd[63:0] = Rs[7:0] Rs[15:8] Rs[23:16] Rs[31:24] Rs[39:32] Rs[47,40] Rs[55,48] Rs[63:56]
void MacroAssembler::revb(Register Rd, Register Rs, Register tmp1, Register tmp2) {
if (UseRVB) {
if (UseZbb) {
rev8(Rd, Rs);
return;
}
Expand All @@ -1570,7 +1570,7 @@ void MacroAssembler::revb(Register Rd, Register Rs, Register tmp1, Register tmp2
// rotate right with shift bits
void MacroAssembler::ror_imm(Register dst, Register src, uint32_t shift, Register tmp)
{
if (UseRVB) {
if (UseZbb) {
rori(dst, src, shift);
return;
}
Expand Down Expand Up @@ -3708,7 +3708,7 @@ void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Regi
// shift 16 bits once.
void MacroAssembler::ctzc_bit(Register Rd, Register Rs, bool isLL, Register tmp1, Register tmp2)
{
if (UseRVB) {
if (UseZbb) {
assert_different_registers(Rd, Rs, tmp1);
int step = isLL ? 8 : 16;
ctz(Rd, Rs);
Expand Down Expand Up @@ -4050,7 +4050,7 @@ void MacroAssembler::zero_memory(Register addr, Register len, Register tmp) {
// shift left by shamt and add
// Rd = (Rs1 << shamt) + Rs2
void MacroAssembler::shadd(Register Rd, Register Rs1, Register Rs2, Register tmp, int shamt) {
if (UseRVB) {
if (UseZba) {
if (shamt == 1) {
sh1add(Rd, Rs1, Rs2);
return;
Expand All @@ -4072,14 +4072,14 @@ void MacroAssembler::shadd(Register Rd, Register Rs1, Register Rs2, Register tmp
}

void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
if (UseRVB) {
if (bits == 16) {
zext_h(dst, src);
return;
} else if (bits == 32) {
zext_w(dst, src);
return;
}
if (UseZba && bits == 32) {
zext_w(dst, src);
return;
}

if (UseZbb && bits == 16) {
zext_h(dst, src);
return;
}

if (bits == 8) {
Expand All @@ -4091,7 +4091,7 @@ void MacroAssembler::zero_extend(Register dst, Register src, int bits) {
}

void MacroAssembler::sign_extend(Register dst, Register src, int bits) {
if (UseRVB) {
if (UseZbb) {
if (bits == 8) {
sext_b(dst, src);
return;
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/riscv.ad
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1483,7 +1483,7 @@ const bool Matcher::match_rule_supported(int opcode) {
case Op_CountLeadingZerosL:
case Op_CountTrailingZerosI:
case Op_CountTrailingZerosL:
return UseRVB;
return UseZbb;
}

return true; // Per default match rules are supported.
Expand Down
Loading

0 comments on commit aee4eea

Please sign in to comment.