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8291893: riscv: remove fence.i used in user space
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8291947: riscv: fail to build after JDK-8290840
8310656: RISC-V: __builtin___clear_cache can fail silently.

Reviewed-by: fyang, luhenry
Backport-of: 5a539e8da7dbea1eaa10d799f75199ea359f7a22
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zifeihan authored and RealFYang committed Mar 29, 2024
1 parent f71648c commit d4b0021
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Showing 12 changed files with 141 additions and 61 deletions.
7 changes: 0 additions & 7 deletions src/hotspot/cpu/riscv/assembler_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -311,13 +311,6 @@ void Assembler::movptr(Register Rd, address addr) {
addi(Rd, Rd, offset);
}

void Assembler::ifence() {
fence_i();
if (UseConservativeFence) {
fence(ir, ir);
}
}

#define INSN(NAME, NEG_INSN) \
void Assembler::NAME(Register Rs, Register Rt, const address &dest) { \
NEG_INSN(Rt, Rs, dest); \
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2 changes: 0 additions & 2 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,6 @@ class Assembler : public AbstractAssembler {
void movptr(Register Rd, address addr);
void movptr_with_offset(Register Rd, address addr, int32_t &offset);
void movptr(Register Rd, uintptr_t imm64);
void ifence();
void j(const address &dest, Register temp = t0);
void j(const Address &adr, Register temp = t0);
void j(Label &l, Register temp = t0);
Expand Down Expand Up @@ -897,7 +896,6 @@ class Assembler : public AbstractAssembler {
emit(insn); \
}

INSN(fence_i, 0b0001111, 0b001, 0b000000000000);
INSN(ecall, 0b1110011, 0b000, 0b000000000000);
INSN(_ebreak, 0b1110011, 0b000, 0b000000000001);

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13 changes: 5 additions & 8 deletions src/hotspot/cpu/riscv/compiledIC_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -69,8 +69,8 @@ address CompiledStaticCall::emit_to_interp_stub(CodeBuffer &cbuf, address mark)
#undef __

int CompiledStaticCall::to_interp_stub_size() {
// fence_i + fence* + (lui, addi, slli, addi, slli, addi) + (lui, addi, slli, addi, slli) + jalr
return NativeFenceI::instruction_size() + 12 * NativeInstruction::instruction_size;
// (lui, addi, slli, addi, slli, addi) + (lui, addi, slli, addi, slli) + jalr
return 12 * NativeInstruction::instruction_size;
}

int CompiledStaticCall::to_trampoline_stub_size() {
Expand All @@ -97,8 +97,7 @@ void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, ad
}

// Creation also verifies the object.
NativeMovConstReg* method_holder
= nativeMovConstReg_at(stub + NativeFenceI::instruction_size());
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub);
#ifndef PRODUCT
NativeGeneralJump* jump = nativeGeneralJump_at(method_holder->next_instruction_address());

Expand All @@ -123,8 +122,7 @@ void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_
address stub = static_stub->addr();
assert(stub != NULL, "stub not found");
// Creation also verifies the object.
NativeMovConstReg* method_holder
= nativeMovConstReg_at(stub + NativeFenceI::instruction_size());
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub);
method_holder->set_data(0);
}

Expand All @@ -141,8 +139,7 @@ void CompiledDirectStaticCall::verify() {
address stub = find_stub(false /* is_aot */);
assert(stub != NULL, "no stub found for static call");
// Creation also verifies the object.
NativeMovConstReg* method_holder
= nativeMovConstReg_at(stub + NativeFenceI::instruction_size());
NativeMovConstReg* method_holder = nativeMovConstReg_at(stub);
NativeJump* jump = nativeJump_at(method_holder->next_instruction_address());

// Verify state.
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3 changes: 1 addition & 2 deletions src/hotspot/cpu/riscv/globals_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -99,8 +99,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, TraceTraps, false, "Trace all traps the signal handler") \
/* For now we're going to be safe and add the I/O bits to userspace fences. */ \
product(bool, UseConservativeFence, true, \
"Extend i for r and o for w in the pred/succ flags of fence;" \
"Extend fence.i to fence.i + fence.") \
"Extend i for r and o for w in the pred/succ flags of fence") \
product(bool, AvoidUnalignedAccesses, true, \
"Avoid generating unaligned memory accesses") \
experimental(bool, UseRVV, false, "Use RVV instructions") \
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21 changes: 19 additions & 2 deletions src/hotspot/cpu/riscv/icache_riscv.cpp
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2023, Rivos Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand All @@ -25,16 +26,32 @@

#include "precompiled.hpp"
#include "asm/macroAssembler.hpp"
#include "riscv_flush_icache.hpp"
#include "runtime/java.hpp"
#include "runtime/icache.hpp"

#define __ _masm->

static int icache_flush(address addr, int lines, int magic) {
os::icache_flush((long int) addr, (long int) (addr + (lines << ICache::log2_line_size)));
// To make a store to instruction memory visible to all RISC-V harts,
// the writing hart has to execute a data FENCE before requesting that
// all remote RISC-V harts execute a FENCE.I.

// We need to make sure stores happens before the I/D cache synchronization.
__asm__ volatile("fence rw, rw" : : : "memory");

RiscvFlushIcache::flush((uintptr_t)addr, ((uintptr_t)lines) << ICache::log2_line_size);

return magic;
}

void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {
// Only riscv_flush_icache is supported as I-cache synchronization.
// We must make sure the VM can execute such without error.
if (!RiscvFlushIcache::test()) {
vm_exit_during_initialization("Unable to synchronize I-cache");
}

address start = (address)icache_flush;
*flush_icache_stub = (ICache::flush_icache_stub_t)start;

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5 changes: 0 additions & 5 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -574,7 +574,6 @@ void MacroAssembler::emit_static_call_stub() {
// CompiledDirectStaticCall::set_to_interpreted knows the
// exact layout of this stub.

ifence();
mov_metadata(xmethod, (Metadata*)NULL);

// Jump to the entry point of the i2c stub.
Expand Down Expand Up @@ -4137,10 +4136,6 @@ void MacroAssembler::cmp_l2i(Register dst, Register src1, Register src2, Registe
bind(done);
}

void MacroAssembler::safepoint_ifence() {
ifence();
}

#ifdef COMPILER2
// short string
// StringUTF16.indexOfChar
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3 changes: 0 additions & 3 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -71,9 +71,6 @@ class MacroAssembler: public Assembler {
atomic_incw(tmp1, tmp2);
}

// Place a fence.i after code may have been modified due to a safepoint.
void safepoint_ifence();

// Alignment
void align(int modulus, int extra_offset = 0);

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9 changes: 0 additions & 9 deletions src/hotspot/cpu/riscv/nativeInst_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,6 @@
// - - NativeIllegalInstruction
// - - NativeCallTrampolineStub
// - - NativeMembar
// - - NativeFenceI

// The base class for different kinds of native instruction abstractions.
// Provides the primitive operations to manipulate code relative to this.
Expand Down Expand Up @@ -553,12 +552,4 @@ inline NativeMembar *NativeMembar_at(address addr) {
return (NativeMembar*)addr;
}

class NativeFenceI : public NativeInstruction {
public:
static inline int instruction_size() {
// 2 for fence.i + fence
return (UseConservativeFence ? 2 : 1) * NativeInstruction::instruction_size;
}
};

#endif // CPU_RISCV_NATIVEINST_RISCV_HPP
4 changes: 0 additions & 4 deletions src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -331,10 +331,6 @@ static void patch_callers_callsite(MacroAssembler *masm) {
__ la_patchable(t0, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)), offset);
__ jalr(x1, t0, offset);

// Explicit fence.i required because fixup_callers_callsite may change the code
// stream.
__ safepoint_ifence();

__ pop_CPU_state();
// restore sp
__ leave();
Expand Down
19 changes: 0 additions & 19 deletions src/hotspot/os_cpu/linux_riscv/os_linux_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -37,23 +37,4 @@
*(jlong *) dst = *(const jlong *) src;
}

// SYSCALL_RISCV_FLUSH_ICACHE is used to flush instruction cache. The "fence.i" instruction
// only work on the current hart, so kernel provides the icache flush syscall to flush icache
// on each hart. You can pass a flag to determine a global or local icache flush.
static void icache_flush(long int start, long int end)
{
const int SYSCALL_RISCV_FLUSH_ICACHE = 259;
register long int __a7 asm ("a7") = SYSCALL_RISCV_FLUSH_ICACHE;
register long int __a0 asm ("a0") = start;
register long int __a1 asm ("a1") = end;
// the flush can be applied to either all threads or only the current.
// 0 means a global icache flush, and the icache flush will be applied
// to other harts concurrently executing.
register long int __a2 asm ("a2") = 0;
__asm__ volatile ("ecall\n\t"
: "+r" (__a0)
: "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a7)
: "memory");
}

#endif // OS_CPU_LINUX_RISCV_VM_OS_LINUX_RISCV_HPP
77 changes: 77 additions & 0 deletions src/hotspot/os_cpu/linux_riscv/riscv_flush_icache.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,77 @@
/*
* Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2023, Rivos Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/

#include "precompiled.hpp"
#include "logging/log.hpp"
#include "riscv_flush_icache.hpp"
#include "runtime/os.hpp"
#include "runtime/vm_version.hpp"
#include "utilities/debug.hpp"

#include <sys/syscall.h>
#include <unistd.h>

#define check_with_errno(check_type, cond, msg) \
do { \
int err = errno; \
check_type(cond, "%s; error='%s' (errno=%s)", msg, os::strerror(err), \
os::errno_name(err)); \
} while (false)

#define assert_with_errno(cond, msg) check_with_errno(assert, cond, msg)
#define guarantee_with_errno(cond, msg) check_with_errno(guarantee, cond, msg)

#ifndef NR_riscv_flush_icache
#ifndef NR_arch_specific_syscall
#define NR_arch_specific_syscall 244
#endif
#define NR_riscv_flush_icache (NR_arch_specific_syscall + 15)
#endif

#define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
#define SYS_RISCV_FLUSH_ICACHE_ALL 0UL

static long sys_flush_icache(uintptr_t start, uintptr_t end , uintptr_t flags) {
return syscall(NR_riscv_flush_icache, start, end, flags);
}

bool RiscvFlushIcache::test() {
ATTRIBUTE_ALIGNED(64) char memory[64];
long ret = sys_flush_icache((uintptr_t)&memory[0],
(uintptr_t)&memory[sizeof(memory) - 1],
SYS_RISCV_FLUSH_ICACHE_ALL);
if (ret == 0) {
return true;
}
int err = errno; \
log_error(os)("Syscall: RISCV_FLUSH_ICACHE not available; error='%s' (errno=%s)",
os::strerror(err), os::errno_name(err));
return false;
}

void RiscvFlushIcache::flush(uintptr_t start, uintptr_t end) {
long ret = sys_flush_icache(start, end, SYS_RISCV_FLUSH_ICACHE_ALL);
guarantee_with_errno(ret == 0, "riscv_flush_icache failed");
}
39 changes: 39 additions & 0 deletions src/hotspot/os_cpu/linux_riscv/riscv_flush_icache.hpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,39 @@
/*
* Copyright (c) 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2023, Rivos Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/

#ifndef OS_LINUX_RISCV_FLUSH_ICACHE_LINUX_HPP
#define OS_LINUX_RISCV_FLUSH_ICACHE_LINUX_HPP

#include "memory/allocation.hpp"
#include "runtime/vm_version.hpp"
#include "utilities/growableArray.hpp"

class RiscvFlushIcache: public AllStatic {
public:
static bool test();
static void flush(uintptr_t start, uintptr_t end);
};

#endif // OS_LINUX_RISCV_FLUSH_ICACHE_LINUX_HPP

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