8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

[DingliZhang]

Please review this backport to riscv-port-jdk17u.
Backport of JDK-8296447.
A little conflict is that we do not have the vneg_v in macroAssembler_riscv.cpp

Tested:

• jdk/incubator/vector (release/fastdebug with UseRVV on QEMU)
• tier1 (release with UseRVV on QEMU)

---

Progress

• Change must be properly reviewed (1 review required, with at least 1 Reviewer)
• Change must not contain extraneous whitespace
• Commit message must refer to an issue

Issue

• JDK-8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

Reviewers

• Fei Yang (@RealFYang - Reviewer)
• Feilong Jiang (@feilongjiang - Author)

Reviewing

Using git

Checkout this PR locally:
$ git fetch https://git.openjdk.org/riscv-port-jdk17u.git pull/41/head:pull/41
$ git checkout pull/41

Update a local copy of the PR:
$ git checkout pull/41
$ git pull https://git.openjdk.org/riscv-port-jdk17u.git pull/41/head

Using Skara CLI tools

Checkout this PR locally:
$ git pr checkout 41

View PR using the GUI difftool:
$ git pr show -t 41

Using diff file

Download this PR as a diff file:
https://git.openjdk.org/riscv-port-jdk17u/pull/41.diff

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Link to Webrev Comment

[bridgekeeper]

👋 Welcome back dzhang! A progress list of the required criteria for merging this PR into riscv-port will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

[openjdk]

This backport pull request has now been updated with issue from the original commit.

[mlbridge]

Webrevs

• 00: Full (5cdb6fc8)

[RealFYang]

Looks good to me.

[openjdk]

@DingliZhang This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

Reviewed-by: fyang, fjiang

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 1 new commit pushed to the riscv-port branch:

• b5dedfe: 8302776: RISC-V: Fix typo CSR_INSTERT to CSR_INSTRET

Please see this link for an up-to-date comparison between the source branch of this pull request and the riscv-port branch.
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@RealFYang) but any other Committer may sponsor as well.

➡️ To flag this PR as ready for integration with the above commit message, type /integrate in a new comment. (Afterwards, your sponsor types /sponsor in a new comment to perform the integration).

[DingliZhang]

/integrate

[openjdk]

@DingliZhang
Your change (at version 5cdb6fc) is now ready to be sponsored by a Committer.

[feilongjiang]

Looks good to me.

[RealFYang]

/sponsor

[openjdk]

Going to push as commit 0884e87.
Since your change was applied there has been 1 commit pushed to the riscv-port branch:

• b5dedfe: 8302776: RISC-V: Fix typo CSR_INSTERT to CSR_INSTRET

Your commit was automatically rebased without conflicts.

[openjdk]

@RealFYang @DingliZhang Pushed as commit 0884e87.

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