8307150: RISC-V: Remove remaining StoreLoad barrier with UseCondCardMark for Serial/Parallel GC

[feilongjiang]

Hi,
Please review this clean backport of JDK-8307150 to riscv-port-jdk17u.
Same as the mainline, this StoreLoad barrier is no longer needed after the removal of CMS.

---

Progress

• Change must not contain extraneous whitespace
• Commit message must refer to an issue

Issue

• JDK-8307150: RISC-V: Remove remaining StoreLoad barrier with UseCondCardMark for Serial/Parallel GC

Reviewers

• Fei Yang (@RealFYang - Reviewer)

Reviewing

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$ git fetch https://git.openjdk.org/riscv-port-jdk17u.git pull/55/head:pull/55
$ git checkout pull/55

Update a local copy of the PR:
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$ git pull https://git.openjdk.org/riscv-port-jdk17u.git pull/55/head

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$ git pr checkout 55

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[bridgekeeper]

👋 Welcome back fjiang! A progress list of the required criteria for merging this PR into riscv-port will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

[openjdk]

This backport pull request has now been updated with issue from the original commit.

[openjdk]

@feilongjiang This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8307150: RISC-V: Remove remaining StoreLoad barrier with UseCondCardMark for Serial/Parallel GC

Reviewed-by: fyang

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 2 new commits pushed to the riscv-port branch:

• c24cc2a: 8301036: RISC-V: Factor out functions baseOffset & baseOffset32 from MacroAssembler
• 1422604: 8297697: RISC-V: Add support for SATP mode detection

Please see this link for an up-to-date comparison between the source branch of this pull request and the riscv-port branch.
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

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[mlbridge]

Webrevs

• 00: Full (e19fb021)

[RealFYang]

OK. We should have this so that we are on-par with other CPUs like aarch64.

[feilongjiang]

@RealFYang -- Thanks for the review.
/integrate

[openjdk]

@feilongjiang
Your change (at version e19fb02) is now ready to be sponsored by a Committer.

[RealFYang]

/sponsor

[openjdk]

Going to push as commit 504014c.
Since your change was applied there have been 2 commits pushed to the riscv-port branch:

• c24cc2a: 8301036: RISC-V: Factor out functions baseOffset & baseOffset32 from MacroAssembler
• 1422604: 8297697: RISC-V: Add support for SATP mode detection

Your commit was automatically rebased without conflicts.

[openjdk]

@RealFYang @feilongjiang Pushed as commit 504014c.

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