8282466: riscv: Remove unused code in linux_riscv

feilongjiang · Yanhong Zhu · commit 579d7c56b0a2 · 2022-03-01T07:21:28.000Z
Reviewed-by: yzhu, fyang
diff --git a/src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp b/src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp
@@ -101,7 +101,7 @@ int AbstractInterpreter::size_activation(int max_stack,
              // frame do we need to allow max_stack words.
              (is_top_frame ? max_stack : temps + extra_args);
 
-  // On riscv64 we always keep the stack pointer 16-aligned, so we
+  // On riscv we always keep the stack pointer 16-aligned, so we
   // must round up here.
   size = align_up(size, 2);
 
diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -3034,7 +3034,7 @@ enum Nf {
     return is_imm_in_range(imm, 12, 0);
   }
 
-  // The maximum range of a branch is fixed for the riscv64
+  // The maximum range of a branch is fixed for the riscv
   // architecture.
   static const unsigned long branch_range = 1 * M;
 
diff --git a/src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp b/src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -261,10 +261,10 @@ int PatchingStub::_patch_info_offset = -NativeGeneralJump::instruction_size;
 
 void PatchingStub::align_patch_site(MacroAssembler* masm) {}
 
-// RISCV64 don't use C1 runtime patching. When need patch, just deoptimize.
+// RISCV don't use C1 runtime patching. When need patch, just deoptimize.
 void PatchingStub::emit_code(LIR_Assembler* ce)
 {
-  assert(false, "RISCV64 should not use C1 runtime patching");
+  assert(false, "RISCV should not use C1 runtime patching");
 }
 
 void DeoptimizeStub::emit_code(LIR_Assembler* ce)
diff --git a/src/hotspot/cpu/riscv/c1_Defs_riscv.hpp b/src/hotspot/cpu/riscv/c1_Defs_riscv.hpp
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -76,7 +76,7 @@ enum {
 
 // Encoding of float value in debug info.  This is true on x86 where
 // floats are extended to doubles when stored in the stack, false for
-// RISCV64 where floats and doubles are stored in their native form.
+// RISCV where floats and doubles are stored in their native form.
 enum {
   pd_float_saved_as_double = false
 };
diff --git a/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp b/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -27,4 +27,4 @@
 //               FpuStackSim
 //--------------------------------------------------------
 
-// No FPU stack on RISCV64
+// No FPU stack on RISCV
diff --git a/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp b/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -26,7 +26,7 @@
 #ifndef CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
 #define CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
 
-// No FPU stack on RISCV64
+// No FPU stack on RISCV
 class FpuStackSim;
 
 #endif // CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
diff --git a/src/hotspot/cpu/riscv/c1_FrameMap_riscv.cpp b/src/hotspot/cpu/riscv/c1_FrameMap_riscv.cpp
@@ -380,7 +380,7 @@ LIR_Opr FrameMap::stack_pointer() {
 
 // JSR 292
 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
-  return LIR_OprFact::illegalOpr;  // Not needed on riscv64
+  return LIR_OprFact::illegalOpr;  // Not needed on riscv
 }
 
 bool FrameMap::validate_frame() {
diff --git a/src/hotspot/cpu/riscv/c1_FrameMap_riscv.hpp b/src/hotspot/cpu/riscv/c1_FrameMap_riscv.hpp
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -26,7 +26,7 @@
 #ifndef CPU_RISCV_C1_FRAMEMAP_RISCV_HPP
 #define CPU_RISCV_C1_FRAMEMAP_RISCV_HPP
 
-//  On RISCV64 the frame looks as follows:
+//  On RISCV the frame looks as follows:
 //
 //  +-----------------------------+---------+----------------------------------------+----------------+-----------
 //  | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
diff --git a/src/hotspot/cpu/riscv/c2_init_riscv.cpp b/src/hotspot/cpu/riscv/c2_init_riscv.cpp
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -28,7 +28,7 @@
 #include "opto/compile.hpp"
 #include "opto/node.hpp"
 
-// processor dependent initialization for riscv64
+// processor dependent initialization for riscv
 
 extern void reg_mask_init();
 
diff --git a/src/hotspot/cpu/riscv/disassembler_riscv.hpp b/src/hotspot/cpu/riscv/disassembler_riscv.hpp
@@ -36,7 +36,7 @@
 
 // Returns address of n-th instruction preceding addr,
 // NULL if no preceding instruction can be found.
-// On (riscv64), we assume a constant instruction length.
+// On riscv, we assume a constant instruction length.
 // It might be beneficial to check "is_readable" as we do on ppc and s390.
 static address find_prev_instr(address addr, int n_instr) {
   return addr - Assembler::instruction_size * n_instr;
diff --git a/src/hotspot/cpu/riscv/frame_riscv.cpp b/src/hotspot/cpu/riscv/frame_riscv.cpp
@@ -388,7 +388,7 @@ void frame::verify_deopt_original_pc(CompiledMethod* nm, intptr_t* unextended_sp
 //------------------------------------------------------------------------------
 // frame::adjust_unextended_sp
 void frame::adjust_unextended_sp() {
-  // On riscv64, sites calling method handle intrinsics and lambda forms are treated
+  // On riscv, sites calling method handle intrinsics and lambda forms are treated
   // as any other call site. Therefore, no special action is needed when we are
   // returning to any of these call sites.
 
@@ -651,7 +651,7 @@ void frame::describe_pd(FrameValues& values, int frame_no) {
 #endif
 
 intptr_t *frame::initial_deoptimization_info() {
-  // Not used on riscv64, but we must return something.
+  // Not used on riscv, but we must return something.
   return NULL;
 }
 
diff --git a/src/hotspot/cpu/riscv/frame_riscv.inline.hpp b/src/hotspot/cpu/riscv/frame_riscv.inline.hpp
@@ -30,7 +30,7 @@
 #include "code/codeCache.hpp"
 #include "code/vmreg.inline.hpp"
 
-// Inline functions for RISCV64 frames:
+// Inline functions for RISCV frames:
 
 // Constructors:
 
diff --git a/src/hotspot/cpu/riscv/interp_masm_riscv.cpp b/src/hotspot/cpu/riscv/interp_masm_riscv.cpp
@@ -224,7 +224,7 @@ void InterpreterMacroAssembler::get_cache_and_index_at_bcp(Register cache,
   get_cache_index_at_bcp(index, bcp_offset, index_size);
   assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below");
   // Convert from field index to ConstantPoolCacheEntry
-  // riscv64 already has the cache in xcpool so there is no need to
+  // riscv already has the cache in xcpool so there is no need to
   // install it in cache. Instead we pre-add the indexed offset to
   // xcpool and return it in cache. All clients of this method need to
   // be modified accordingly.
diff --git a/src/hotspot/cpu/riscv/matcher_riscv.hpp b/src/hotspot/cpu/riscv/matcher_riscv.hpp
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2021, Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2021, 2022, Huawei Technologies Co., Ltd. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -38,7 +38,7 @@
     return UseRVV;
   }
 
-  // riscv64 supports misaligned vectors store/load.
+  // riscv supports misaligned vectors store/load.
   static constexpr bool misaligned_vectors_ok() {
     return true;
   }
diff --git a/src/hotspot/cpu/riscv/nativeInst_riscv.cpp b/src/hotspot/cpu/riscv/nativeInst_riscv.cpp
@@ -353,7 +353,7 @@ void NativeJump::patch_verified_entry(address entry, address verified_entry, add
 
   assert(nativeInstruction_at(verified_entry)->is_jump_or_nop() ||
          nativeInstruction_at(verified_entry)->is_sigill_zombie_not_entrant(),
-         "riscv64 cannot replace non-jump with jump");
+         "riscv cannot replace non-jump with jump");
 
   // Patch this nmethod atomically.
   if (Assembler::reachable_from_branch_at(verified_entry, dest)) {
diff --git a/src/hotspot/cpu/riscv/nativeInst_riscv.hpp b/src/hotspot/cpu/riscv/nativeInst_riscv.hpp
@@ -234,7 +234,7 @@ inline NativeInstruction* nativeInstruction_at(address addr) {
   return (NativeInstruction*)addr;
 }
 
-// The natural type of an RISCV64 instruction is uint32_t
+// The natural type of an RISCV instruction is uint32_t
 inline NativeInstruction* nativeInstruction_at(uint32_t *addr) {
   return (NativeInstruction*)addr;
 }
@@ -246,7 +246,7 @@ inline NativeCall* nativeCall_at(address addr);
 
 class NativeCall: public NativeInstruction {
  public:
-  enum RISCV64_specific_constants {
+  enum RISCV_specific_constants {
     instruction_size            =    4,
     instruction_offset          =    0,
     displacement_offset         =    0,
@@ -330,7 +330,7 @@ inline NativeCall* nativeCall_before(address return_address) {
 // (used to manipulate inlined 64-bit data calls, etc.)
 class NativeMovConstReg: public NativeInstruction {
  public:
-  enum RISCV64_specific_constants {
+  enum RISCV_specific_constants {
     movptr_instruction_size             =    6 * NativeInstruction::instruction_size, // lui, addi, slli, addi, slli, addi.  See movptr().
     movptr_with_offset_instruction_size =    5 * NativeInstruction::instruction_size, // lui, addi, slli, addi, slli. See movptr_with_offset().
     load_pc_relative_instruction_size   =    2 * NativeInstruction::instruction_size, // auipc, ld
@@ -396,7 +396,7 @@ inline NativeMovConstReg* nativeMovConstReg_before(address addr) {
   return test;
 }
 
-// RISCV64 should not use C1 runtime patching, so just leave NativeMovRegMem Unimplemented.
+// RISCV should not use C1 runtime patching, so just leave NativeMovRegMem Unimplemented.
 class NativeMovRegMem: public NativeInstruction {
  public:
   int instruction_start() const {
@@ -434,7 +434,7 @@ inline NativeMovRegMem* nativeMovRegMem_at (address addr) {
 
 class NativeJump: public NativeInstruction {
  public:
-  enum RISCV64_specific_constants {
+  enum RISCV_specific_constants {
     instruction_size            =    NativeInstruction::instruction_size,
     instruction_offset          =    0,
     data_offset                 =    0,
@@ -468,7 +468,7 @@ inline NativeJump* nativeJump_at(address addr) {
 
 class NativeGeneralJump: public NativeJump {
 public:
-  enum RISCV64_specific_constants {
+  enum RISCV_specific_constants {
     instruction_size            =    6 * NativeInstruction::instruction_size, // lui, addi, slli, addi, slli, jalr
     instruction_offset          =    0,
     data_offset                 =    0,
@@ -507,7 +507,7 @@ inline bool NativeInstruction::is_jump_or_nop() {
 class NativeCallTrampolineStub : public NativeInstruction {
  public:
 
-  enum RISCV64_specific_constants {
+  enum RISCV_specific_constants {
     // Refer to function emit_trampoline_stub.
     instruction_size = 3 * NativeInstruction::instruction_size + wordSize, // auipc + ld + jr + target address
     data_offset      = 3 * NativeInstruction::instruction_size,            // auipc + ld + jr
diff --git a/src/hotspot/cpu/riscv/register_riscv.hpp b/src/hotspot/cpu/riscv/register_riscv.hpp
@@ -97,7 +97,7 @@ class RegisterImpl: public AbstractRegisterImpl {
 
 REGISTER_IMPL_DECLARATION(Register, RegisterImpl, RegisterImpl::number_of_registers);
 
-// The integer registers of the RISCV64 architecture
+// The integer registers of the RISCV architecture
 
 CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
 
@@ -188,7 +188,7 @@ class FloatRegisterImpl: public AbstractRegisterImpl {
 
 REGISTER_IMPL_DECLARATION(FloatRegister, FloatRegisterImpl, FloatRegisterImpl::number_of_registers);
 
-// The float registers of the RISCV64 architecture
+// The float registers of the RISCV architecture
 
 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1));
 
diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
diff --git a/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp
diff --git a/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp
diff --git a/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp b/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp
diff --git a/src/hotspot/os_cpu/linux_riscv/globals_linux_riscv.hpp b/src/hotspot/os_cpu/linux_riscv/globals_linux_riscv.hpp
diff --git a/src/hotspot/os_cpu/linux_riscv/thread_linux_riscv.hpp b/src/hotspot/os_cpu/linux_riscv/thread_linux_riscv.hpp

Original file line number	Diff line number	Diff line change
`@@ -3034,7 +3034,7 @@ enum Nf {`
`3034`	`3034`	`return is_imm_in_range(imm, 12, 0);`
`3035`	`3035`	`}`
`3036`	`3036`
`3037`		`- // The maximum range of a branch is fixed for the riscv64`
	`3037`	`+ // The maximum range of a branch is fixed for the riscv`
`3038`	`3038`	`// architecture.`
`3039`	`3039`	`static const unsigned long branch_range = 1 * M;`
`3040`	`3040`
Original file line number	Diff line number	Diff line change
`@@ -1,7 +1,7 @@`
`1`	`1`	`/*`
`2`	`2`	`* Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.`
`3`	`3`	`* Copyright (c) 2014, Red Hat Inc. All rights reserved.`
`4`		`- * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.`
	`4`	`+ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.`
`5`	`5`	`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.`
`6`	`6`	`*`
`7`	`7`	`* This code is free software; you can redistribute it and/or modify it`
`@@ -261,10 +261,10 @@ int PatchingStub::_patch_info_offset = -NativeGeneralJump::instruction_size;`
`261`	`261`
`262`	`262`	`void PatchingStub::align_patch_site(MacroAssembler* masm) {}`
`263`	`263`
`264`		`-// RISCV64 don't use C1 runtime patching. When need patch, just deoptimize.`
	`264`	`+// RISCV don't use C1 runtime patching. When need patch, just deoptimize.`
`265`	`265`	`void PatchingStub::emit_code(LIR_Assembler* ce)`
`266`	`266`	`{`
`267`		`- assert(false, "RISCV64 should not use C1 runtime patching");`
	`267`	`+ assert(false, "RISCV should not use C1 runtime patching");`
`268`	`268`	`}`
`269`	`269`
`270`	`270`	`void DeoptimizeStub::emit_code(LIR_Assembler* ce)`
Original file line number	Diff line number	Diff line change
`@@ -380,7 +380,7 @@ LIR_Opr FrameMap::stack_pointer() {`
`380`	`380`
`381`	`381`	`// JSR 292`
`382`	`382`	`LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {`
`383`		`- return LIR_OprFact::illegalOpr; // Not needed on riscv64`
	`383`	`+ return LIR_OprFact::illegalOpr; // Not needed on riscv`
`384`	`384`	`}`
`385`	`385`
`386`	`386`	`bool FrameMap::validate_frame() {`