8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

[yadongw]

This bug can be reproduced by java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:

For the
sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and
SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores,
backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.

It may cause an unspecified behaviour depends on specific hardware implementations.

---

Progress

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Issue

• JDK-8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

Reviewers

• Fei Yang (@RealFYang - Reviewer)

Reviewing

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$ git fetch https://git.openjdk.java.net/riscv-port pull/17/head:pull/17
$ git checkout pull/17

Update a local copy of the PR:
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$ git pr checkout 17

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Download this PR as a diff file:
https://git.openjdk.java.net/riscv-port/pull/17.diff

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[mlbridge]

Webrevs

• 00: Full (4a88b0cb)

[RealFYang]

Looks good. Thanks for fixing this :-)

[openjdk]

@yadongw This change now passes all automated pre-integration checks.

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8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

Reviewed-by: fyang

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[yadongw]

/integrate

[openjdk]

@yadongw
Your change (at version 4a88b0c) is now ready to be sponsored by a Committer.

[RealFYang]

/sponsor

[openjdk]

Going to push as commit 5bb7f8b.

[openjdk]

@RealFYang @yadongw Pushed as commit 5bb7f8b.

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[zhengxiaolinX]

Thank you for fixing this. Qemu and C910 cannot reveal this issue so I didn't notice it. :-(
I just tested this -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 on both a D1 and an unleashed board, and this issue was reproduced without this patch.

No need to reply -- it is just a comment.