This repository contains an OpenRISC 1000 compliant processor IP core.
It is written in Verilog HDL.
This repository only contains the IP source code and some documentation. For a verification environment, please see other projects.
The documentation is located in the doc/ directory.
It is asciidoc format, and there's a makefile in there to build HTML or PDF. To build the HTML documentation, run the following in the doc/ directory:
It is licensed under the Open Hardware Description License (OHDL). For details please see the LICENSE file or http://juliusbaxter.net/ohdl/