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mor1kx - an OpenRISC 1000 processor IP core
Verilog SystemVerilog

pic: fix OPTION_PIC_TRIGGER="EDGE"

As pointed out in github issue #29, clearing an edge triggered
interrupt while the interrupt source is still high would
re-trigger the interrupt even though no new edge has
occurred.

This cures this by adding an additional registering
of the irq_unmasked signals and only set the picsr
spr register when an edge occurs.

Also, the priority between setting and clearing the
bits in picsr have been reversed.
latest commit 6caa7dba90
@skristiansson skristiansson authored
Failed to load latest commit information.
bench/verilog Debug: Execution traceport
doc replace missing'
rtl/verilog pic: fix OPTION_PIC_TRIGGER="EDGE"
LICENSE Add copy of OHDL in LICENSE file
README.pod Add README.pod

README.pod

mor1kx - an OpenRISC processor IP core

The Basics

This repository contains an OpenRISC 1000 compliant processor IP core.

It is written in Verilog HDL.

This repository only contains the IP source code and some documentation. For a verification environment, please see other projects.

Documentation

The documentation is located in the doc/ directory.

It is asciidoc format, and there's a makefile in there to build HTML or PDF. To build the HTML documentation, run the following in the doc/ directory:

  make html

License

It is licensed under the Open Hardware Description License (OHDL). For details please see the LICENSE file or http://juliusbaxter.net/ohdl/

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