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Merge pull request #77 from stffrdhrn/fusesoc-ci

Fusesoc CI
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stffrdhrn committed Mar 7, 2019
2 parents aa4ea5a + 705e33a commit 84b96767c0ccc2a0004c5e0a47626a6657b78021
@@ -1,22 +1,59 @@
language: c
cache: ccache
sudo: true
dist: trusty

addons:
apt:
packages:
- build-essential
- git
- curl
- libelf-dev
- flex
- bison
- autoconf
- python3-pip

before_install:
- cd /tmp
- git clone http://git.veripool.org/git/verilator
- cd verilator
- git checkout verilator_3_902
- autoconf
- ./configure
- make
- sudo make install
- cd $TRAVIS_BUILD_DIR
- sudo pip3 install --upgrade pip setuptools
- sudo pip3 install --ignore-installed six
- sudo pip3 install fusesoc

install:
- .travis/install-${JOB}.sh

script:
- verilator --lint-only rtl/verilog/*.v +incdir+rtl/verilog
- export PIPELINE=${P}
- export EXPECTED_FAILURES=${EF}
- export EXTRA_CORE_ARGS=${EXTRA}
- .travis/run-${JOB}.sh

matrix:
fast_finish: true

jobs:
allow_failures:
- env: JOB=or1k-tests SIM=icarus P=ESPRESSO
include:
- stage: verilator
env: JOB=verilator
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy" EXTRA="--feature_dmmu NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy or1k-dsxinsn" EXTRA="--feature_immu NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy" EXTRA="--feature_datacache NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy" EXTRA="--feature_instructioncache NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy" EXTRA="--feature_debugunit NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy or1k-cmov" EXTRA="--feature_cmov NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=CAPPUCCINO EF="or1k-cy or1k-ext" EXTRA="--feature_ext NONE"
- stage: testing
env: JOB=or1k-tests SIM=icarus P=ESPRESSO

@@ -0,0 +1,41 @@
# dockerfile to simulate the travis environment only for testing purposes,
# this is not actually used in travis
#
# to use:
# sudo docker build -t travis-mor1kx .travis/
# sudo docker run -it --rm -v ${PWD}:/tmp/src/cores/mor1kx:Z travis-mor1kx
# $ .travis/install-or1k-tests.sh && .travis/run-or1k-tests.sh
#
# tip:
# If you only want to test the run-*.sh scripts and find install takes too
# long you can add 'RUN .travis/install-or1k-tests.sh' and
# 'RUN .travis/install-verilator.sh' to this dockerfile to have an image
# with the full environment already installed.
#
FROM ubuntu:trusty
RUN apt-get update && apt-get install -y \
build-essential \
autoconf \
git \
curl \
python3-pip \
libelf-dev \
flex bison

RUN sudo pip3 install --upgrade pip setuptools
RUN sudo pip3 install --ignore-installed six
RUN sudo pip3 install fusesoc

RUN groupadd -g 999 travis && \
useradd -m -r -u 999 -g travis travis
USER travis

RUN mkdir -p /tmp/src/cores/mor1kx
VOLUME /tmp/src/cores/mor1kx
ENV TRAVIS_BUILD_DIR=/tmp/src/cores/mor1kx
WORKDIR /tmp/src/cores/mor1kx

ENV PIPELINE=CAPPUCCINO
ENV SIM=icarus

LABEL maintainer Stafford Horne <shorne@gmail.com>
@@ -0,0 +1,18 @@
#!/bin/sh

set -x

mkdir -p $HOME/src/tools
mkdir -p $HOME/tools

# Get iverilog latest source, the version in trusty is no good
cd $HOME/src/tools
curl --remote-name --location \
http://shorne.noip.me/downloads/verilog-10.2.tar.gz
tar xf verilog-10.2.tar.gz
cd verilog-10.2
./configure --prefix=$HOME/tools
make -j2
make install


@@ -0,0 +1,31 @@
#!/bin/sh

set -x

mkdir -p $HOME/src/tools
mkdir -p $HOME/tools

# Install the required sim
$TRAVIS_BUILD_DIR/.travis/install-${SIM}.sh

# Get our toolchain
cd $HOME/src/tools
curl --remote-name --location \
https://github.com/stffrdhrn/gcc/releases/download/or1k-9.0.0-20181113/or1k-elf-9.0.0-20181112.tar.xz
tar xC $HOME/tools -f $HOME/src/tools/or1k-elf-9.0.0-20181112.tar.xz

PATH="$HOME/tools/or1k-elf/bin:${PATH}"
export PATH

# Download and compile or1k-tests
cd $HOME/src/tools
git clone https://github.com/openrisc/or1k-tests.git ;\
cd or1k-tests/native
make -j2

# Setup fusesoc and add the cores required by or1k-tests
fusesoc init -y
fusesoc library add mor1kx-generic https://github.com/stffrdhrn/mor1kx-generic.git
fusesoc library add intgen https://github.com/stffrdhrn/intgen.git
fusesoc library add mor1kx $TRAVIS_BUILD_DIR

@@ -0,0 +1,19 @@
#!/bin/sh

set -x

mkdir -p $HOME/src/tools
mkdir -p $HOME/tools

# Get required version of verilator
cd $HOME/src/tools

git clone http://git.veripool.org/git/verilator
cd verilator
git checkout verilator_3_902

autoconf
./configure --prefix=$HOME/tools
make -j2
make install

@@ -0,0 +1,23 @@
#!/bin/sh

set -x

PATH="$HOME/tools/or1k-elf/bin:${PATH}"
PATH="$HOME/tools/bin:${PATH}"
export PATH

# allow overriding root dir if we aren't running in travis
if [ -z $OR1K_TESTS_ROOT ] ; then
OR1K_TESTS_ROOT=$HOME/src/tools/or1k-tests
fi

cd $OR1K_TESTS_ROOT/native
export CORE_ARGS="--pipeline=$PIPELINE $EXTRA_CORE_ARGS"
export SIM_ARGS="--sim=$SIM"
./runtests.sh $@
result=$?

if [ $result != 0 ] ; then
cat runtests.log
fi
exit $result
@@ -0,0 +1,5 @@
#!/bin/sh

export PATH=$HOME/tools/bin:$PATH

verilator --lint-only rtl/verilog/*.v +incdir+rtl/verilog
@@ -141,3 +141,37 @@ as running Linux) requires a setting different than the default value.*
|FEATURE_CUST6|Enable the `l.cust*` custom instruction|`NONE`|`ENABLED` `NONE`| |
|FEATURE_CUST7|Enable the `l.cust*` custom instruction|`NONE`|`ENABLED` `NONE`| |
|FEATURE_CUST8|Enable the `l.cust*` custom instruction|`NONE`|`ENABLED` `NONE`| |

## Testing and Continuous Integration

A CPU core cannot be trusted without a full set of verification testing. The `mor1kx`
pipelines are constantly verified for correctness with the or1k Continuous
Integration (CI) suite running in [travis ci](travis-ci.org). This currently covers:

- source linting - a `verilator --lint-only` check is run on each commit to
ensure there are no code quality issues.
- [or1k-tests](https://github.com/openrisc/or1k-tests) - the `or1k-tests` test suite
is run against each pipeline to check most major instructions, exception handling,
caching, timers, interrupts and other features.

Status: [![Build Status](https://travis-ci.org/openrisc/mor1kx.svg?branch=master)](https://travis-ci.org/openrisc/mor1kx)

In the future we are working on bringing more tests including:

- softfloat, fpu verification (may not be feasable in CI due to long run times)
- CPU pipeline debugging verification via GDB/OpenOCD
- Resource utilization regression with yosys synth_intel synth_xilinx
- Formal verification with yosys
- Verification that each revision can boot differnt OS's **Linux**, **RTMES**
- Golden reference `or1ksim` trace comparisons vs verilog model using constrained
random inputs.

Verification status of mor1kx pipelines:

|Pipeline|Testing Support|Comments|
|--------|---------------|--------|
|`CAPPUCCINO`|`Linting` `or1k-tests`|All supported tests passing|
|`ESPRESSO`|`linting` `or1k-tests` |Still many pipeline failures, see issue #71|
|`PRONTO_ESPRESSO`|`linting`|No toolchain support for no-delayslot c code|
|`MAROCCHINO`|`linting` `or1k-tests`|See [marocchino](https://github.com/openrisc/or1k_marocchino) project.|

@@ -25,15 +25,14 @@
`ifndef CPU_WRAPPER
`define CPU_WRAPPER `MOR1KX_INST.mor1kx_cpu
`endif
`define CPU_INST `CPU_WRAPPER.`MOR1KX_CPU_PIPELINE.mor1kx_cpu
`define EXECUTE_STAGE_INSN `CPU_WRAPPER.monitor_execute_insn
`define EXECUTE_STAGE_ADV `CPU_WRAPPER.monitor_execute_advance
`define CPU_clk `CPU_WRAPPER.monitor_clk
`define CPU_FLAG `CPU_WRAPPER.monitor_flag
`define CPU_SR `CPU_WRAPPER.monitor_spr_sr
`define EXECUTE_PC `CPU_WRAPPER.monitor_execute_pc
`define GPR_GET(x) `CPU_INST.get_gpr(x)
`define GPR_SET(x, y) `CPU_INST.set_gpr(x, y)
`define GPR_GET(x) `CPU_WRAPPER.monitor.get_gpr(x)
`define GPR_SET(x, y) `CPU_WRAPPER.monitor.set_gpr(x, y)

`include "mor1kx-defines.v"

@@ -198,6 +198,58 @@ module mor1kx_cpu
wire [OPTION_OPERAND_WIDTH-1:0] monitor_spr_esr/* verilator public */;
wire monitor_branch_mispredict/* verilator public */;

// synthesis translate_off
`ifndef SYNTHESIS
/* Provide interface hooks for register functions. */
generate
if (OPTION_CPU=="CAPPUCCINO") begin : monitor

`include "mor1kx_utils.vh"
localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
OPTION_RF_NUM_SHADOW_GPR);

function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
// verilator public
input [RF_ADDR_WIDTH-1:0] gpr_num;
get_gpr = cappuccino.mor1kx_cpu.get_gpr(gpr_num);
endfunction
task set_gpr;
// verilator public
input [RF_ADDR_WIDTH-1:0] gpr_num;
input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
cappuccino.mor1kx_cpu.set_gpr(gpr_num, gpr_value);
endtask
end
if (OPTION_CPU=="ESPRESSO") begin : monitor
function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
// verilator public
input [15:0] gpr_num;
get_gpr = espresso.mor1kx_cpu.get_gpr(gpr_num);
endfunction
task set_gpr;
// verilator public
input [15:0] gpr_num;
input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
espresso.mor1kx_cpu.set_gpr(gpr_num, gpr_value);
endtask
end
/* verilator lint_off WIDTH */
if (OPTION_CPU=="PRONTO_ESPRESSO") begin : monitor
function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
// verilator public
input [15:0] gpr_num;
get_gpr = prontoespresso.mor1kx_cpu.get_gpr(gpr_num);
endfunction
task set_gpr;
// verilator public
input [15:0] gpr_num;
input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
prontoespresso.mor1kx_cpu.set_gpr(gpr_num, gpr_value);
endtask
end
endgenerate
`endif
// synthesis translate_on

generate
/* verilator lint_off WIDTH */
@@ -331,7 +383,7 @@ module mor1kx_cpu
.snoop_adr_i (snoop_adr_i[31:0]),
.snoop_en_i (snoop_en_i));

// synthesis translate_off
// synthesis translate_off
`ifndef SYNTHESIS

assign monitor_flag = monitor_flag_set ? 1 :
@@ -358,8 +410,9 @@ module mor1kx_cpu

assign monitor_execute_insn = monitor_execute_insn_reg;


`endif
// synthesis translate_on
// synthesis translate_on


end // block: cappuccino

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