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cappuccino: add DSX support

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1 parent ef69546 commit e78995b7a22b4ecc7545988f8704188598f9e919 @juliusbaxter juliusbaxter committed Oct 6, 2012
Showing with 5 additions and 2 deletions.
  1. +2 −1 rtl/verilog/mor1kx_cpu_cappuccino.v
  2. +3 −1 rtl/verilog/mor1kx_ctrl_cappuccino.v
@@ -735,7 +735,8 @@ module mor1kx_cpu_cappuccino
.FEATURE_MAC(FEATURE_MAC),
.FEATURE_SYSCALL(FEATURE_SYSCALL),
.FEATURE_TRAP(FEATURE_TRAP),
- .FEATURE_RANGE(FEATURE_RANGE)
+ .FEATURE_RANGE(FEATURE_RANGE),
+ .FEATURE_DSX(FEATURE_DSX)
)
mor1kx_ctrl_cappuccino
(/*AUTOINST*/
@@ -510,6 +510,8 @@ module mor1kx_ctrl_cappuccino
spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0;
if (FEATURE_IMMU!="NONE")
spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0;
+ if (FEATURE_DSX!="NONE")
+ spr_sr[`OR1K_SPR_SR_DSX ] <= ctrl_delay_slot;
end
else if (padv_ctrl)
begin
@@ -554,10 +556,10 @@ module mor1kx_ctrl_cappuccino
spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ];
spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ];
-
end
else if (op_rfe)
spr_sr <= spr_esr;
+
end // if (padv_ctrl)
// Exception SR

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