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cappuccino: add DSX support

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commit e78995b7a22b4ecc7545988f8704188598f9e919 1 parent ef69546
Julius Baxter authored October 06, 2012
3  rtl/verilog/mor1kx_cpu_cappuccino.v
@@ -735,7 +735,8 @@ module mor1kx_cpu_cappuccino
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        .FEATURE_MAC(FEATURE_MAC),
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        .FEATURE_SYSCALL(FEATURE_SYSCALL),
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        .FEATURE_TRAP(FEATURE_TRAP),
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-       .FEATURE_RANGE(FEATURE_RANGE)
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+       .FEATURE_RANGE(FEATURE_RANGE),
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+       .FEATURE_DSX(FEATURE_DSX)
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        )
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      mor1kx_ctrl_cappuccino 
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      (/*AUTOINST*/
4  rtl/verilog/mor1kx_ctrl_cappuccino.v
@@ -510,6 +510,8 @@ module mor1kx_ctrl_cappuccino
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 	    spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0;
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 	  if (FEATURE_IMMU!="NONE")
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 	    spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0;
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+          if (FEATURE_DSX!="NONE")
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+	    spr_sr[`OR1K_SPR_SR_DSX ] <= ctrl_delay_slot;
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        end
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      else if (padv_ctrl)
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        begin
@@ -554,10 +556,10 @@ module mor1kx_ctrl_cappuccino
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 		 spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ];
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 	       spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ];
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-
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 	    end
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 	  else if (op_rfe)
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 	    spr_sr <= spr_esr;
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+	  
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        end // if (padv_ctrl)
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    // Exception SR

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