Skip to content
Browse files

(1) Fix bug. Prevent decode_rf_wb for FP32 comparisons. (2) Set defau…

…lt mask (if masked FPU flags extension is used) for FPU flags to zero in according with discussion in http://opencores.org/or1k/Architecture_Specification#FPCSR_Extension
  • Loading branch information...
1 parent 69b97fc commit 15a8a24755e900ba03b38115baaf3813a22b5f24 @bandvig bandvig committed Mar 8, 2016
Showing with 5 additions and 4 deletions.
  1. +2 −2 rtl/verilog/mor1kx-sprs.v
  2. +3 −1 rtl/verilog/mor1kx_decode.v
  3. +0 −1 rtl/verilog/mor1kx_execute_alu.v
View
4 rtl/verilog/mor1kx-sprs.v
@@ -335,8 +335,8 @@
`define OR1K_FPCSR_MASK_DZF 20
// bus select
`define OR1K_FPCSR_MASK_ALL `OR1K_FPCSR_MASK_DZF:`OR1K_FPCSR_MASK_OVF
-// reset value. enables: dzf,inf,ivf,snf,ovf
-`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'b1_1100_0101
+// reset value.
+`define OR1K_FPCSR_MASK_RESET_VALUE `OR1K_FPCSR_ALLF_SIZE'd0
// Implementation-specific SPR defines
View
4 rtl/verilog/mor1kx_decode.v
@@ -287,7 +287,9 @@ module mor1kx_decode
// All '11????' opcodes except l.sfxx and l.mtspr
(decode_insn_i[31:30] == 2'b11 &
!(opc_insn == `OR1K_OPCODE_SF |
- decode_op_mtspr_o | decode_op_lsu_store_o));
+ decode_op_mtspr_o | decode_op_lsu_store_o) &
+ !((FEATURE_FPU != "NONE") &
+ (opc_insn == `OR1K_OPCODE_FPU) & decode_insn_i[3]));
// Register file addresses
assign decode_rfa_adr_o = decode_insn_i[`OR1K_RA_SELECT];
View
1 rtl/verilog/mor1kx_execute_alu.v
@@ -776,7 +776,6 @@ endgenerate
op_movhi_i ? immediate_i :
op_mul_i ? mul_result[OPTION_OPERAND_WIDTH-1:0] :
fpu_arith_valid ? fpu_result :
- fpu_cmp_valid ? {OPTION_OPERAND_WIDTH{1'b0}} :
op_shift_i ? shift_result :
op_div_i ? div_result :
op_ffl1_i ? ffl1_result :

0 comments on commit 15a8a24

Please sign in to comment.
Something went wrong with that request. Please try again.