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Commits on Mar 8, 2016
  1. @bandvig

    (1) Fix bug. Prevent decode_rf_wb for FP32 comparisons. (2) Set defau…

    bandvig committed Mar 8, 2016
    …lt mask (if masked FPU flags extension is used) for FPU flags to zero in according with discussion in http://opencores.org/or1k/Architecture_Specification#FPCSR_Extension
Commits on Nov 3, 2015
  1. @skristiansson
Commits on Oct 16, 2015
  1. @olofk

    Silence some synthesis warnings

    olofk committed Oct 16, 2015
Commits on Sep 1, 2015
  1. @wallento

    Merge pull request #31 from imphil/master

    wallento committed Sep 1, 2015
    Use variables after they have been defined
  2. @imphil

    Use variables after they have been defined

    imphil committed Sep 1, 2015
    This bug was found by ModelSim:
    
    ** Error:
    mor1kx_lsu_cappuccino.v(249):
    (vlog-2730) Undefined variable: 'state'.
    ** Error:
    mor1kx_lsu_cappuccino.v(249):
    (vlog-2730) Undefined variable: 'WRITE'.
    ** Error:
    mor1kx_lsu_cappuccino.v(353):
    'WRITE' already declared in this scope.
    ** Error:
    mor1kx_lsu_cappuccino.v(357):
    'state' already declared in this scope (mor1kx_lsu_cappuccino).
Commits on May 14, 2015
  1. @skristiansson

    pic: fix OPTION_PIC_TRIGGER="EDGE"

    skristiansson committed May 14, 2015
    As pointed out in github issue #29, clearing an edge triggered
    interrupt while the interrupt source is still high would
    re-trigger the interrupt even though no new edge has
    occurred.
    
    This cures this by adding an additional registering
    of the irq_unmasked signals and only set the picsr
    spr register when an edge occurs.
    
    Also, the priority between setting and clearing the
    bits in picsr have been reversed.
  2. @skristiansson
Commits on Mar 8, 2015
  1. @skristiansson

    immu: move tlb_reload_pagefault back into its always block

    skristiansson committed Mar 8, 2015
    tlb_reload_pagefault is written on other occasions than on
    reset and tlb_reload_pagefault_clear_i in the hw reload
    statemachine.
  2. @bandvig
Commits on Mar 6, 2015
  1. @skristiansson
  2. @bandvig @skristiansson

    add fpu32 support

    bandvig committed with skristiansson Mar 5, 2015
    To use the FPU:
    (1) add all files from verilog/pfpu32 folder into your project
    (2) add .FEATURE_FPU("ENABLED") to the parameter list of mor1kx instance
    Comparison with OR1200's FPU.
    Operation clock cost for: ADD/SUB - MUL - DIV - I2F/F2I
    Port of OR1200 FPU 8 - 36 - 35 - 6
    Pipelined FPU 5 - 6 - 18 - 3
    Size of standalone FPU (LUTs as logic, Spartan6, ISE14.6):
    Port of OR1200 FPU : 2966 / 96 MHz
    Pipelined FPU
    DSP blocks arn't used : 2822 / 112 MHz
    DSP blocks are used : 1554 / 76 MHz (+5 DSP modules)
    Performance gain by Whetstone benchmark is up to 2 ... 3.5 times
    against OR1200's FPU and up to 20 times against soft-float
    depending on test.
    
    Additionally there is an extension to FPCSR.
    Thanks to the extension the each of FPU's exceptions could be
    masked separately.
    The extension is disabled by default till approve from community.
    The extension is activated by uncommenting the
    OR1K_FPCSR_MASK_FLAGS macro in mor1kx-sprs.v
Commits on Feb 20, 2015
  1. @skristiansson

    cappuccino: add support for l.msync

    skristiansson committed Feb 20, 2015
    Since stores can be postponed when the store buffer is
    activated, l.msync should ensure a memory barrier and stall
    the pipeline until all the stores in the storebuffer are
    completed.
Commits on Feb 4, 2015
  1. @olofk

    Add option to clear RF in simulations

    olofk committed Feb 4, 2015
    When building against FPGA targets, we can often assume that internal
    memories are cleared after power-on and some (buggy) software relies
    on that. This adds a parameter to initialize the RF to zero for
    RTL simulations.
    
    Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
Commits on Feb 2, 2015
  1. @olofk

    Move localparam definition out from generate loops

    olofk committed Feb 2, 2015
    Xilinx ISE doesn't like defining localparams inside of generate
    loops.
Commits on Dec 21, 2014
  1. @skristiansson

    immu: add support for multiway tlb

    skristiansson committed Dec 22, 2014
    Limitied to software refill so far
  2. @skristiansson

    dmmu: add support for multiway tlb

    skristiansson committed Dec 22, 2014
    Limitied to software refill so far
Commits on Dec 13, 2014
  1. @skristiansson
  2. @skristiansson

    Bump version number to 4.0

    skristiansson committed Dec 13, 2014
Commits on Nov 12, 2014
  1. @andrewray
  2. @skristiansson

    cappuccino/lsu: properly handle async reset for atomic_reserve

    skristiansson committed Nov 12, 2014
    Based on a suggestion by Andrew Ray
Commits on Oct 21, 2014
  1. @skristiansson

    cappuccino/rf: *really* fix RF_ADDR_WIDTH

    skristiansson committed Oct 21, 2014
    As Stefan W pointed out to me, my previous fix
    was completely incorrect and only correctly for
    OPTION_RF_NUM_SHADOW_GPR = 1.
    This is based on a patch he presented, but makes
    use of the `clog2 macro to maintain compatibility with
    icarus.
    
    Also, remove the unused RF_WORDS localparam.
  2. @skristiansson

    steal utils from orpsoc-cores

    skristiansson committed Oct 21, 2014
    This makes a copy of the orpsoc-cores verilog_utils
    core.
    For now, the reason is to gain access to the clog2
    logic from that, but the other functions are copied in
    here as well.
  3. @wallento
  4. @skristiansson

    cappuccino/rf: fix RF_ADDR_WIDTH

    skristiansson committed Oct 21, 2014
    The address width should increase by one bit for each
    gpr file, not get multiplied.
  5. @olofk @skristiansson

    cappuccino/rf: zero pad rf read addresses

    olofk committed with skristiansson Oct 21, 2014
    To match the address space when shadowed GPR files are enabled.
  6. @wallento
  7. @wallento

    Fix store buffer RAM pointer sizes

    wallento committed Oct 21, 2014
    The pointers' highest bit is not part of the address (but used for
    full signaling). The port of the RAM is one bit less.
Commits on Oct 16, 2014
  1. @skristiansson
  2. @wallento @skristiansson

    Debug: Execution traceport

    wallento committed with skristiansson Apr 28, 2014
    The execution traceport traces all executed program counters, the
    respective instruction and accesses to the register file with this
    instruction. A rudimentary set of trace actions can be implemented in
    a synthesizable way.
    
    Set FEATURE_TRACEPORT_EXEC="ENABLED" to enable this trace port.
    
    Add monitor for simulation.
  3. @skristiansson

    cappuccino/lsu: abort cache refill on snoop hit

    skristiansson committed Aug 26, 2014
    Even though the assumption that the bus accesses from the refill
    and the snoop are excelusive, there is a possibility that a
    refill have been initiated at the same time as the snoop bus
    access is going on.
    This doesn't cause problems as long as the refill happens
    to to the way that is being snooped, but if the snoop occurs to
    an opposite way, the refill logic has saved the the old
    tag data for that way and will write it back once the refill
    has finished.
    
    This avoids the issue by aborting refills when there's
    a snoop hit, and prevents refills to be started at the
    same instant as the snoop access and the snoop hit is handled.
    
    This can be improved upon in several ways, either by only
    aborting/preventing the accesses that are related to the
    refill or as an even cleaner solution by splitting the tags
    into seperate memories, so the tag saving mechanism can be
    removed.
    
    The overhead of aborting all refills on snoop-hits is however
    rather small, since the refill would anyway be stalling waiting
    for the snooped access to finish, so for now it will suffice as
    a solution.
    
    Conflicts:
    	rtl/verilog/mor1kx_lsu_cappuccino.v
  4. @skristiansson

    cappuccino/lsu: break atomic link when snoop occurs at the same time …

    skristiansson committed Aug 19, 2014
    …as load
    
    This fixes a corner case where the snoop occurs at the exact
    time as the load.
  5. @skristiansson

    squash to coherency

    skristiansson committed Oct 16, 2014
  6. @skristiansson

    cappuccino: check atomic_reserve at end of storebuffer

    skristiansson committed Jun 1, 2014
    Since there might be a snooped access while the atomic store
    (l.swa) is in the storebuffer, the atomic_reserve flag has to
    be checked right when the l.swa is coming out from the
    store buffer and let out on the bus.
    
    This achieves this by stalling the pipeline while the
    l.swa is in the store buffer.
    
    There are a couple of reasons why the atomic goes through
    the store buffer and not bypass it.
    1) It simplifies some of the logic (less special cases)
    2) The store buffer should have knowledge about atomic stores
       going through it, since it place restrictions on what kind
       of re-ordering can be done.
       The current simple store buffer does no such things,
       but this way we are a little more future-proof.
  7. @wallento @skristiansson

    DCache: Coherency

    wallento committed with skristiansson Jun 20, 2014
    This adds coherency via the snoop port.
    
    The cache have a duplicate tag memory for snooping,
    which significantly improve performance over the other
    alternative where the normal tag memory is used.
    
    Note by Stefan Kristiansson:
    This commit message is an excerpt of the original message
    and the commit itself is squashed together from a couple
    of trial and errors, but I think it should be
    pretty representive of the gist of the original patch.
  8. @wallento @skristiansson

    Add snoop port

    wallento committed with skristiansson Apr 28, 2014
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