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PCU: fix reset and SPR write #47

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merged 2 commits into from Feb 12, 2017
Merged

PCU: fix reset and SPR write #47

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3e7db0c
pcu: fix reset
jordens Feb 11, 2017
1b51259
pcu: fix spr writes
jordens Feb 11, 2017
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12 changes: 6 additions & 6 deletions rtl/verilog/mor1kx_pcu.v
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Expand Up @@ -88,15 +88,15 @@ module mor1kx_pcu
for(pcu_num = 0; pcu_num < OPTION_PERFCOUNTERS_NUM + 1; pcu_num = pcu_num + 1) begin: pcu_generate
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
pcu_pccr[pcu_num] = 32'd0;
pcu_pcmr[pcu_num] = 32'd0 | 1 << `OR1K_PCMR_CP;
pcu_pccr[pcu_num] <= 32'd0;
pcu_pcmr[pcu_num] <= 32'd0 | 1 << `OR1K_PCMR_CP;
// we could write pcu registers only in system mode
end else if (spr_we_i && spr_sys_mode_i) begin
if (pcu_pccr_access)
pcu_pccr[spr_addr_i[2:0]] <= spr_dat_i;
if (pcu_pccr_access & (spr_addr_i[2:0] == pcu_num))
pcu_pccr[pcu_num] <= spr_dat_i;
// WPE are not implemented, hence we do not update WPE part
if (pcu_pcmr_access) begin
pcu_pcmr[spr_addr_i[2:0]][`OR1K_PCMR_DDS:`OR1K_PCMR_CISM] <=
if (pcu_pcmr_access && (spr_addr_i[2:0] == pcu_num)) begin
pcu_pcmr[pcu_num][`OR1K_PCMR_DDS:`OR1K_PCMR_CISM] <=
spr_dat_i[`OR1K_PCMR_DDS:`OR1K_PCMR_CISM];
end else if (((pcu_pcmr[pcu_num][`OR1K_PCMR_CISM] & spr_sys_mode_i) |
(pcu_pcmr[pcu_num][`OR1K_PCMR_CIUM] & ~spr_sys_mode_i))) begin
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