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Added new simple MAC test to ORPSoC test suite:

* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests
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julius committed Sep 9, 2010
1 parent 6bc497d commit 57a449d24d4e0bc41a5d233fe84d339a42f9d40c
Showing with 14 additions and 6 deletions.
  1. +14 −6 rtl/verilog/or1200_mult_mac.v
@@ -117,13 +117,13 @@ reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [2*width-1:0] mac_r;
reg [63:0] mac_r;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [2*width-1:0] mac_r;
wire [63:0] mac_r;
wire [width-1:0] x;
wire [width-1:0] y;
@@ -175,7 +175,7 @@ assign alu_op_div_divu = 1'b0;
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
always @(alu_op or mul_prod_r or mac_r or a or b)
always @*
casex(alu_op) // synopsys parallel_case
`OR1200_ALUOP_DIV: begin
@@ -253,15 +253,23 @@ assign mul_prod_r = {2*width{1'b0}};


// Signal to indicate when we should check for new MAC op
reg ex_freeze_r;

always @(posedge clk or posedge rst)
if (rst)
ex_freeze_r <= 1'b1;
ex_freeze_r <= ex_freeze;

// Propagation of l.mac opcode
// Propagation of l.mac opcode, only register it for one cycle
always @(posedge clk or posedge rst)
if (rst)
mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
mac_op_r1 <= mac_op;
mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;

// Propagation of l.mac opcode

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