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or1200: the infamous l.rfe fix, and bug fix for when multiply is disa…

…bled
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julius
julius committed Sep 1, 2011
1 parent a4a0015 commit f0255fab7de3cd72c248f6075e0876affaa6625b
Showing with 8 additions and 3 deletions.
  1. +2 −0 rtl/verilog/or1200_ctrl.v
  2. +6 −3 rtl/verilog/or1200_mult_mac.v
@@ -438,6 +438,8 @@ always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.rfe
`OR1200_OR32_RFE,
// l.mfspr
`OR1200_OR32_MFSPR:
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
@@ -112,11 +112,11 @@ module or1200_mult_mac(
//
reg [width-1:0] result;
reg ex_freeze_r;
wire alu_op_mul;
wire alu_op_smul;
`ifdef OR1200_MULT_IMPLEMENTED
reg [2*width-1:0] mul_prod_r;
wire alu_op_smul;
wire alu_op_umul;
wire alu_op_mul;
`ifdef OR1200_MULT_SERIAL
reg [5:0] serial_mul_cnt;
reg mul_free;
@@ -170,7 +170,10 @@ module or1200_mult_mac(
assign alu_op_smul = (alu_op == `OR1200_ALUOP_MUL);
assign alu_op_umul = (alu_op == `OR1200_ALUOP_MULU);
assign alu_op_mul = alu_op_smul | alu_op_umul;
`endif
`else
assign alu_op_smul = 0;
assign alu_op_mul = 0;
`endif
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];

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