From d63dbacfa244e643a3680aaaa262da3c063b460e Mon Sep 17 00:00:00 2001
From: Andrey Bacherov <bandvig@mail.ru>
Date: Mon, 27 Jul 2020 17:05:08 +0300
Subject: [PATCH] Fixes proposed by Athanasios Moschos
 (https://github.com/0ena). (1) Add "or1k_defines.v" include into
 or1k_marocchino_monitor.v (2) Move qm_r declaration before 1st usage in
 pfpu_marocchino_div.v. Both the issues cause error in Modelsim.

---
 bench/verilog/or1k_marocchino_monitor.v           | 2 ++
 rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/bench/verilog/or1k_marocchino_monitor.v b/bench/verilog/or1k_marocchino_monitor.v
index fe61a48..30afd55 100644
--- a/bench/verilog/or1k_marocchino_monitor.v
+++ b/bench/verilog/or1k_marocchino_monitor.v
@@ -22,6 +22,8 @@
 //                                                                    //
 ////////////////////////////////////////////////////////////////////////
 
+`include "or1k_defines.v"
+
 /* Configure these defines to point to the marocchino instantiation */
 `ifndef OR1K_INST
  `define OR1K_INST dut.gencpu.or1k_marocchino0
diff --git a/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v b/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v
index 9ac64ff..3218d4c 100644
--- a/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v
+++ b/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v
@@ -187,6 +187,8 @@ module r4div_fract58
   // signed digits to tow's complement on the fly converter
   //  # part Q
   reg   [N-1:0] q_r;
+  //  # part QM
+  reg   [N-1:0] qm_r;
   //  # ---
   always @(posedge cpu_clk) begin
     if (div_start_i)
@@ -204,8 +206,6 @@ module r4div_fract58
       endcase
     end
   end // @clock
-  //  # part QM
-  reg   [N-1:0] qm_r;
   //  # ---
   always @(posedge cpu_clk) begin
     if (div_start_i)