realtek: new device support ZyXEL XGS1210-12

The ZyXEL XGS1210-12 is a 8x1GBit, 2x2.5GBit and 2x10GBit SFP+
switch. The device has the following hardware:
    - RTL9302B SoC
    - Macronix MX25L12833F (16MB flash)
    - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
    - RTL8231 GPIO extender to control the port LEDs
    - RTL8218D 8x Gigabit PHY
    - 2 RTL8226 2.5 Gigabit PHYs
The 2 SFP+ uplink ports are not supported by the realtek switch driver, yet.
The bi-color and tri-color (for the 2.5 Gig ports) LEDs are driven directly by
the SoC. A reset button is present on the front but not supported.
Behind the air-vents on the right a 3.3V uart header is externally accessible.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via
115200 baud.

To install, boot into u-boot, halt via pressing <ESC>, load initramfs via tftp
and boot via bootm.
Installation to flash was not tested.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>

target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12.dts

@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "zyxel,xgs1210-12", "realtek,rtl838x-soc";
+	model = "Zyxel XGS1210-12 Switch";
+
+	// mw.l 0xb8003308 0x00200000 active low toggles PHY reset
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+};
+
+&spi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0xe0000>;
+				read-only;
+			};
+			partition@e0000 {
+				label = "u-boot-env";
+				reg = <0xe0000 0x10000>;
+				read-only;
+			};
+			partition@f0000 {
+				label = "u-boot-env2";
+				reg = <0xf0000 0x10000>;
+				read-only;
+			};
+			partition@100000 {
+				label = "jffs";
+				reg = <0x100000 0x100000>;
+			};
+			partition@200000 {
+				label = "jffs2";
+				reg = <0x200000 0x100000>;
+			};
+			partition@300000 {
+				label = "firmware";
+				reg = <0x300000 0xd00000>;
+				compatible = "denx,uimage";
+			};
+		};
+	};
+};
+
+&ethernet0 {
+	mdio: mdio-bus {
+		compatible = "realtek,rtl838x-mdio";
+		regmap = <&ethernet0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* External RTL8218D PHY */
+		EXTERNAL_PHY(0)
+		EXTERNAL_PHY(1)
+		EXTERNAL_PHY(2)
+		EXTERNAL_PHY(3)
+		EXTERNAL_PHY(4)
+		EXTERNAL_PHY(5)
+		EXTERNAL_PHY(6)
+		EXTERNAL_PHY(7)
+
+		/* External RTL8226B PHYs */
+		phy24: ethernet-phy@24 {
+			reg = <24>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+		};
+
+		phy25: ethernet-phy@25 {
+			reg = <25>;
+			compatible = "ethernet-phy-ieee802.3-c45";
+		};
+	};
+};
+
+&switch0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		SWITCH_PORT(0, 1, qsgmii)
+		SWITCH_PORT(1, 2, qsgmii)
+		SWITCH_PORT(2, 3, qsgmii)
+		SWITCH_PORT(3, 4, qsgmii)
+		SWITCH_PORT(4, 5, qsgmii)
+		SWITCH_PORT(5, 6, qsgmii)
+		SWITCH_PORT(6, 7, qsgmii)
+		SWITCH_PORT(7, 8, qsgmii)
+
+		SWITCH_PORT(24, 9, qsgmii)
+		SWITCH_PORT(25, 10, qsgmii)
+
+		/* CPU Port */
+		port@28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};

target/linux/realtek/image/Makefile

@@ -93,4 +93,12 @@ define Device/zyxel_gs1900-8hp-v2
 endef
 TARGET_DEVICES += zyxel_gs1900-8hp-v2
 
+define Device/zyxel_xgs1210-12
+  SOC := rtl9302
+  UIMAGE_MAGIC := 0x93001210
+  DEVICE_VENDOR := Zyxel
+  DEVICE_MODEL := XGS1210-12
+endef
+TARGET_DEVICES += zyxel_xgs1210-12
+
 $(eval $(call BuildImage))