MFC: r340495

- Restore setting the clock for devices which support the default/legacy
  transfer mode only (lost with r321385). [1]
- Similarly, don't try to set the power class on MMC devices that comply
  to version 4.0 of the system specification but are operated in default/
  legacy transfer or 1-bit bus mode as no power class is specified for
  these cases. Trying to set a power class nevertheless resulted in an -
  albeit harmless - error message.

PR:	231713 [1]

sys/dev/mmc/mmc.c

@@ -828,9 +828,14 @@ mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar)
 	const uint8_t *ext_csd;
 	uint32_t clock;
 	uint8_t value;
+	enum mmc_bus_timing timing;
+	enum mmc_bus_width bus_width;
 
 	dev = sc->dev;
-	if (mmcbr_get_mode(dev) != mode_mmc || ivar->csd.spec_vers < 4)
+	timing = mmcbr_get_timing(dev);
+	bus_width = ivar->bus_width;
+	if (mmcbr_get_mode(dev) != mode_mmc || ivar->csd.spec_vers < 4 ||
+	    timing == bus_timing_normal || bus_width == bus_width_1)
 		return (MMC_ERR_NONE);
 
 	value = 0;
@@ -841,8 +846,8 @@ mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar)
 		if (clock <= MMC_TYPE_HS_26_MAX)
 			value = ext_csd[EXT_CSD_PWR_CL_26_195];
 		else if (clock <= MMC_TYPE_HS_52_MAX) {
-			if (mmcbr_get_timing(dev) >= bus_timing_mmc_ddr52 &&
-			    ivar->bus_width >= bus_width_4)
+			if (timing >= bus_timing_mmc_ddr52 &&
+			    bus_width >= bus_width_4)
 				value = ext_csd[EXT_CSD_PWR_CL_52_195_DDR];
 			else
 				value = ext_csd[EXT_CSD_PWR_CL_52_195];
@@ -861,13 +866,13 @@ mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar)
 		if (clock <= MMC_TYPE_HS_26_MAX)
 			value = ext_csd[EXT_CSD_PWR_CL_26_360];
 		else if (clock <= MMC_TYPE_HS_52_MAX) {
-			if (mmcbr_get_timing(dev) == bus_timing_mmc_ddr52 &&
-			    ivar->bus_width >= bus_width_4)
+			if (timing == bus_timing_mmc_ddr52 &&
+			    bus_width >= bus_width_4)
 				value = ext_csd[EXT_CSD_PWR_CL_52_360_DDR];
 			else
 				value = ext_csd[EXT_CSD_PWR_CL_52_360];
 		} else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) {
-			if (ivar->bus_width == bus_width_8)
+			if (bus_width == bus_width_8)
 				value = ext_csd[EXT_CSD_PWR_CL_200_360_DDR];
 			else
 				value = ext_csd[EXT_CSD_PWR_CL_200_360];
@@ -879,7 +884,7 @@ mmc_set_power_class(struct mmc_softc *sc, struct mmc_ivars *ivar)
 		return (MMC_ERR_INVALID);
 	}
 
-	if (ivar->bus_width == bus_width_8)
+	if (bus_width == bus_width_8)
 		value = (value & EXT_CSD_POWER_CLASS_8BIT_MASK) >>
 		    EXT_CSD_POWER_CLASS_8BIT_SHIFT;
 	else
@@ -2165,7 +2170,7 @@ mmc_calculate_clock(struct mmc_softc *sc)
 	for (i = 0; i < sc->child_count; i++) {
 		ivar = device_get_ivars(sc->child_list[i]);
 		if ((ivar->timings & ~(1 << bus_timing_normal)) == 0)
-			continue;
+			goto clock;
 
 		rca = ivar->rca;
 		if (mmc_select_card(sc, rca) != MMC_ERR_NONE) {
@@ -2231,6 +2236,7 @@ mmc_calculate_clock(struct mmc_softc *sc)
 			}
 		}
 
+clock:
 		/* Set clock (must be done before initial tuning). */
 		mmcbr_set_clock(dev, max_dtr);
 		mmcbr_update_ios(dev);