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46 Open 60 Closed
46 Open 60 Closed
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Issues list

verilating compute_tile with 4GB RAM
#191 opened Mar 16, 2022 by hchenji
VCS Compilation Errors
#190 opened Nov 7, 2020 by deadspace99
1
optimsoc & synopsys vcs and DC; packet format change to 10 bit src/dst
#189 opened Nov 3, 2020 by hchenji
9
osd-target-run: error while loading shared libraries: libczmq.so.3: cannot open shared object file: No such file or directory type:question
#186 opened Dec 21, 2019 by IMVector
6
libosd: Unable to open connection to device (-1)
#179 opened Apr 26, 2019 by Theldus
1
Build Script UnicodeEncodeError
#177 opened Apr 11, 2019 by koenenwmn
Fix lint issues after mor1kx update
#172 opened Feb 22, 2019 by imphil
Avoid deadlocks caused by packets exceeding the MP buffer size
#167 opened Feb 19, 2019 by koenenwmn
5
Add cocotb tests for NoC primitives good first issue
#166 opened Feb 12, 2019 by imphil
Accomodating additional features: bootrom, cache
#164 opened Feb 4, 2019 by SRQ91
1
Remove bin2vmem prio:p3 type:janitor
#158 opened Jan 3, 2019 by imphil
@wallento
3
Fix Verilator lint warnings in compute_tile_sim good first issue
#152 opened Nov 12, 2018 by imphil
MP: Messages with negative numbers in them are not received?
#133 opened Aug 19, 2018 by imphil
Make MAM a real bus master prio:p2 type:feature
#131 opened May 29, 2018 by imphil
@wallento
Issue with instantiating mpbuffer
#130 opened May 22, 2018 by bsrivalli3012
1
Integrate Ethernet work by Dominik
#125 opened Apr 23, 2018 by imphil
@koenenwmn
4
Implement communication channel from host to compute tiles type:feature
#124 opened Apr 21, 2018 by imphil
NoC: Let mux overwrite the class on the fly and re-visit the class concept prio:p2 type:idea
#120 opened Mar 27, 2018 by wallento
Change NoC packet format prio:p2 type:feature
#119 opened Mar 27, 2018 by wallento
1
Evaluate use of System Verilog interfaces or struct and unify wiring prio:p3 type:janitor
#118 opened Mar 27, 2018 by wallento
Circular loop through mpbuffer status:on-hold type:bug
#112 opened Mar 12, 2018 by imphil
2
Reduce number of control sets in 2x2 CCCC Nexys4 DDR design prio:p3 type:bug
#111 opened Mar 7, 2018 by imphil
1
Mention the need for compatible requirements in the development docs
#108 opened Mar 1, 2018 by imphil
Setup time violation @ 100 MHz starting at noc_buffer.out_valid prio:p2 status:on-hold type:bug
#104 opened Feb 19, 2018 by koenenwmn
3
Disable reporting of "ignoring assertion" warnings in Vivado prio:p3 type:feature
#101 opened Jan 27, 2018 by imphil
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