{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"VerilogGenerator","owner":"OpenIC-SIG","isFork":false,"description":"A Python VerilogGenerator","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-11-26T01:34:33.880Z"}},{"type":"Public","name":"HDLBits-Chinese-gitbook","owner":"OpenIC-SIG","isFork":false,"description":"","allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":11,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-24T01:21:53.257Z"}}],"repositoryCount":2,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}